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d3dcompiler: Make set_parse_status() more general.
2012-05-08 16:17:30 +02:00
/*
d3dx9: Implement D3DXAssembleShader function, really basic shader assembler. Currently it only accepts a minimal subset of the syntax (e.g. just an instruction and two register types supported) and doesn't produce any real output (i.e. shader bytecode).
2010-03-28 21:16:09 +02:00
* Direct3D shader assembler
*
* Copyright 2008 Stefan Dösinger
* Copyright 2009 Matteo Bruni
*
* This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU Lesser General Public
* License as published by the Free Software Foundation; either
* version 2.1 of the License, or (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public
* License along with this library; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA
*/
%{
#include "config.h"
#include "wine/port.h"
#include "wine/debug.h"
d3dcompiler: Move shader assembler implementation from d3dx9_36.
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#include "d3dcompiler_private.h"
d3dx9: Implement D3DXAssembleShader function, really basic shader assembler. Currently it only accepts a minimal subset of the syntax (e.g. just an instruction and two register types supported) and doesn't produce any real output (i.e. shader bytecode).
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WINE_DEFAULT_DEBUG_CHANNEL(asmshader);
struct asm_parser asm_ctx;
d3dcompiler: Generalize message reporting function.
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void asmparser_message(struct asm_parser *ctx, const char *fmt, ...)
{
d3dcompiler_43: Move asmparser_message() and asmshader_error() up to avoid forward declarations.
2010-09-13 10:45:14 +02:00
va_list args;
d3dcompiler: Generalize message reporting function.
2012-05-08 16:17:31 +02:00
va_start(args, fmt);
compilation_message(&ctx->messages, fmt, args);
va_end(args);
d3dcompiler_43: Move asmparser_message() and asmshader_error() up to avoid forward declarations.
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}
d3dcompiler_43: Make asmshader_error() and set_rel_reg() static.
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static void asmshader_error(char const *s) {
d3dcompiler_43: Move asmparser_message() and asmshader_error() up to avoid forward declarations.
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asmparser_message(&asm_ctx, "Line %u: Error \"%s\" from bison\n", asm_ctx.line_no, s);
d3dcompiler: Make set_parse_status() more general.
2012-05-08 16:17:30 +02:00
set_parse_status(&asm_ctx.status, PARSE_ERR);
d3dcompiler_43: Move asmparser_message() and asmshader_error() up to avoid forward declarations.
2010-09-13 10:45:14 +02:00
}
d3dx9: Implement D3DXAssembleShader function, really basic shader assembler. Currently it only accepts a minimal subset of the syntax (e.g. just an instruction and two register types supported) and doesn't produce any real output (i.e. shader bytecode).
2010-03-28 21:16:09 +02:00
d3dcompiler_43: Make asmshader_error() and set_rel_reg() static.
2010-09-13 10:45:39 +02:00
static void set_rel_reg(struct shader_reg *reg, struct rel_reg *rel) {
d3dx9: Add relative addressing support to the shader assembler.
2010-05-05 19:55:26 +02:00
/* We can have an additional offset without true relative addressing
* ex. c2[ 4 ] */
reg->regnum += rel->additional_offset;
if(!rel->has_rel_reg) {
reg->rel_reg = NULL;
} else {
d3dcompiler: Rename asm_alloc/realloc/free functions to more generic names.
2012-05-08 16:17:32 +02:00
reg->rel_reg = d3dcompiler_alloc(sizeof(*reg->rel_reg));
d3dx9: Add relative addressing support to the shader assembler.
2010-05-05 19:55:26 +02:00
if(!reg->rel_reg) {
return;
}
reg->rel_reg->type = rel->type;
d3dcompiler_43: Don't use nameless unions in our private structures to avoid trouble with compilers where they are not supported.
2010-08-29 23:40:33 +02:00
reg->rel_reg->u.swizzle = rel->swizzle;
d3dx9: Add relative addressing support to the shader assembler.
2010-05-05 19:55:26 +02:00
reg->rel_reg->regnum = rel->rel_regnum;
}
d3dx9: Implement D3DXAssembleShader function, really basic shader assembler. Currently it only accepts a minimal subset of the syntax (e.g. just an instruction and two register types supported) and doesn't produce any real output (i.e. shader bytecode).
2010-03-28 21:16:09 +02:00
}
d3dcompiler_43: Move asmparser_message() and asmshader_error() up to avoid forward declarations.
2010-09-13 10:45:14 +02:00
/* Needed lexer functions declarations */
int asmshader_lex(void);
d3dx9: Implement D3DXAssembleShader function, really basic shader assembler. Currently it only accepts a minimal subset of the syntax (e.g. just an instruction and two register types supported) and doesn't produce any real output (i.e. shader bytecode).
2010-03-28 21:16:09 +02:00
%}
%union {
d3dx9: Add relative addressing support to the shader assembler.
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struct {
float val;
BOOL integer;
} immval;
d3dx9: Add DEFB instruction support in the shader assembler. This completes vs_3_0 assembler language support.
2010-05-14 17:21:42 +02:00
BOOL immbool;
d3dx9: Implement D3DXAssembleShader function, really basic shader assembler. Currently it only accepts a minimal subset of the syntax (e.g. just an instruction and two register types supported) and doesn't produce any real output (i.e. shader bytecode).
2010-03-28 21:16:09 +02:00
unsigned int regnum;
struct shader_reg reg;
d3dx9: Add source register modifiers (sm 2+) support to the shader assembler.
2010-04-21 16:15:46 +02:00
DWORD srcmod;
d3dx9: Add swizzle and writemask support to the shader assembler.
2010-04-21 16:15:46 +02:00
DWORD writemask;
d3dx9: Implement D3DXAssembleShader function, really basic shader assembler. Currently it only accepts a minimal subset of the syntax (e.g. just an instruction and two register types supported) and doesn't produce any real output (i.e. shader bytecode).
2010-03-28 21:16:09 +02:00
struct {
DWORD writemask;
d3dx9: Add swizzle and writemask support to the shader assembler.
2010-04-21 16:15:46 +02:00
DWORD idx;
DWORD last;
} wm_components;
d3dx9: Implement D3DXAssembleShader function, really basic shader assembler. Currently it only accepts a minimal subset of the syntax (e.g. just an instruction and two register types supported) and doesn't produce any real output (i.e. shader bytecode).
2010-03-28 21:16:09 +02:00
DWORD swizzle;
d3dx9: Add swizzle and writemask support to the shader assembler.
2010-04-21 16:15:46 +02:00
struct {
DWORD swizzle;
DWORD idx;
} sw_components;
DWORD component;
d3dx9: Implement D3DXAssembleShader function, really basic shader assembler. Currently it only accepts a minimal subset of the syntax (e.g. just an instruction and two register types supported) and doesn't produce any real output (i.e. shader bytecode).
2010-03-28 21:16:09 +02:00
struct {
DWORD mod;
DWORD shift;
} modshift;
d3dx9: Add other flow control instructions in the shader assembler.
2009-11-24 02:08:32 +01:00
BWRITER_COMPARISON_TYPE comptype;
d3dx9: Add output dcl instruction partial support to the shader assembler.
2010-05-13 17:21:58 +02:00
struct {
DWORD dclusage;
unsigned int regnum;
} declaration;
d3dx9: Add sampler dcl instruction support to the shader assembler.
2010-05-13 17:21:59 +02:00
BWRITERSAMPLER_TEXTURE_TYPE samplertype;
d3dx9: Implement D3DXAssembleShader function, really basic shader assembler. Currently it only accepts a minimal subset of the syntax (e.g. just an instruction and two register types supported) and doesn't produce any real output (i.e. shader bytecode).
2010-03-28 21:16:09 +02:00
struct rel_reg rel_reg;
struct src_regs sregs;
}
/* Common instructions between vertex and pixel shaders */
d3dx9: Support some more vs_3_0 instructions in the shader assembler.
2010-05-05 20:21:10 +02:00
%token INSTR_ADD
%token INSTR_NOP
d3dx9: Implement D3DXAssembleShader function, really basic shader assembler. Currently it only accepts a minimal subset of the syntax (e.g. just an instruction and two register types supported) and doesn't produce any real output (i.e. shader bytecode).
2010-03-28 21:16:09 +02:00
%token INSTR_MOV
d3dx9: Support some more vs_3_0 instructions in the shader assembler.
2010-05-05 20:21:10 +02:00
%token INSTR_SUB
%token INSTR_MAD
%token INSTR_MUL
%token INSTR_RCP
%token INSTR_RSQ
%token INSTR_DP3
%token INSTR_DP4
%token INSTR_MIN
%token INSTR_MAX
%token INSTR_SLT
%token INSTR_SGE
%token INSTR_ABS
%token INSTR_EXP
%token INSTR_LOG
%token INSTR_EXPP
%token INSTR_LOGP
%token INSTR_DST
%token INSTR_LRP
%token INSTR_FRC
%token INSTR_POW
%token INSTR_CRS
%token INSTR_SGN
%token INSTR_NRM
%token INSTR_SINCOS
%token INSTR_M4x4
%token INSTR_M4x3
%token INSTR_M3x4
%token INSTR_M3x3
%token INSTR_M3x2
d3dx9: Add output dcl instruction partial support to the shader assembler.
2010-05-13 17:21:58 +02:00
%token INSTR_DCL
d3dx9: Add DEF instruction support in the shader assembler.
2010-05-14 17:21:42 +02:00
%token INSTR_DEF
d3dx9: Add DEFB instruction support in the shader assembler. This completes vs_3_0 assembler language support.
2010-05-14 17:21:42 +02:00
%token INSTR_DEFB
d3dx9: Add DEFI instruction support in the shader assembler.
2010-05-14 17:21:42 +02:00
%token INSTR_DEFI
d3dx9: Support some flow control instructions in the shader assembler.
2010-05-11 20:29:07 +02:00
%token INSTR_REP
%token INSTR_ENDREP
%token INSTR_IF
%token INSTR_ELSE
%token INSTR_ENDIF
%token INSTR_BREAK
d3dx9: Add predicate support to the shader assembler.
2010-05-11 20:29:07 +02:00
%token INSTR_BREAKP
d3dx9: Support some flow control instructions in the shader assembler.
2010-05-11 20:29:07 +02:00
%token INSTR_CALL
%token INSTR_CALLNZ
%token INSTR_LOOP
%token INSTR_RET
%token INSTR_ENDLOOP
%token INSTR_LABEL
d3dx9: Add predicate support to the shader assembler.
2010-05-11 20:29:07 +02:00
%token INSTR_SETP
d3dx9: Support some more vs_3_0 instructions in the shader assembler.
2010-05-05 20:21:10 +02:00
%token INSTR_TEXLDL
/* Vertex shader only instructions */
%token INSTR_LIT
%token INSTR_MOVA
d3dx9: Implement D3DXAssembleShader function, really basic shader assembler. Currently it only accepts a minimal subset of the syntax (e.g. just an instruction and two register types supported) and doesn't produce any real output (i.e. shader bytecode).
2010-03-28 21:16:09 +02:00
d3dx9: Add ps_3_0 instructions parsing to the shader assembler.
2010-05-19 14:57:38 +02:00
/* Pixel shader only instructions */
d3dx9: Add ps_1_4 instructions parsing to the shader assembler.
2010-07-20 15:01:16 +02:00
%token INSTR_CND
d3dx9: Add ps_3_0 instructions parsing to the shader assembler.
2010-05-19 14:57:38 +02:00
%token INSTR_CMP
%token INSTR_DP2ADD
d3dx9: Add <= ps_1_3 instruction parsing to the shader assembler.
2010-07-21 17:07:24 +02:00
%token INSTR_TEXCOORD
d3dx9: Add ps_1_4 instructions parsing to the shader assembler.
2010-07-20 15:01:16 +02:00
%token INSTR_TEXCRD
d3dx9: Add ps_3_0 instructions parsing to the shader assembler.
2010-05-19 14:57:38 +02:00
%token INSTR_TEXKILL
d3dx9: Add <= ps_1_3 instruction parsing to the shader assembler.
2010-07-21 17:07:24 +02:00
%token INSTR_TEX
d3dx9: Add ps_3_0 instructions parsing to the shader assembler.
2010-05-19 14:57:38 +02:00
%token INSTR_TEXLD
d3dx9: Add <= ps_1_3 instruction parsing to the shader assembler.
2010-07-21 17:07:24 +02:00
%token INSTR_TEXBEM
%token INSTR_TEXBEML
%token INSTR_TEXREG2AR
%token INSTR_TEXREG2GB
%token INSTR_TEXREG2RGB
%token INSTR_TEXM3x2PAD
%token INSTR_TEXM3x2TEX
%token INSTR_TEXM3x3PAD
%token INSTR_TEXM3x3SPEC
%token INSTR_TEXM3x3VSPEC
%token INSTR_TEXM3x3TEX
%token INSTR_TEXDP3TEX
%token INSTR_TEXM3x2DEPTH
%token INSTR_TEXDP3
%token INSTR_TEXM3x3
d3dx9: Add ps_1_4 instructions parsing to the shader assembler.
2010-07-20 15:01:16 +02:00
%token INSTR_TEXDEPTH
%token INSTR_BEM
d3dx9: Add ps_3_0 instructions parsing to the shader assembler.
2010-05-19 14:57:38 +02:00
%token INSTR_DSX
%token INSTR_DSY
%token INSTR_TEXLDP
%token INSTR_TEXLDB
%token INSTR_TEXLDD
d3dx9: Add ps_1_4 instructions parsing to the shader assembler.
2010-07-20 15:01:16 +02:00
%token INSTR_PHASE
d3dx9: Add ps_3_0 instructions parsing to the shader assembler.
2010-05-19 14:57:38 +02:00
d3dx9: Implement D3DXAssembleShader function, really basic shader assembler. Currently it only accepts a minimal subset of the syntax (e.g. just an instruction and two register types supported) and doesn't produce any real output (i.e. shader bytecode).
2010-03-28 21:16:09 +02:00
/* Registers */
%token <regnum> REG_TEMP
d3dx9: Support all the remaining register types in the shader assembler.
2010-05-05 16:56:09 +02:00
%token <regnum> REG_OUTPUT
%token <regnum> REG_INPUT
d3dx9: Implement D3DXAssembleShader function, really basic shader assembler. Currently it only accepts a minimal subset of the syntax (e.g. just an instruction and two register types supported) and doesn't produce any real output (i.e. shader bytecode).
2010-03-28 21:16:09 +02:00
%token <regnum> REG_CONSTFLOAT
d3dx9: Support all the remaining register types in the shader assembler.
2010-05-05 16:56:09 +02:00
%token <regnum> REG_CONSTINT
%token <regnum> REG_CONSTBOOL
%token <regnum> REG_TEXTURE
%token <regnum> REG_SAMPLER
%token <regnum> REG_TEXCRDOUT
%token REG_OPOS
%token REG_OFOG
%token REG_OPTS
%token <regnum> REG_VERTEXCOLOR
%token <regnum> REG_FRAGCOLOR
%token REG_FRAGDEPTH
%token REG_VPOS
%token REG_VFACE
%token REG_ADDRESS
%token REG_LOOP
%token REG_PREDICATE
%token <regnum> REG_LABEL
d3dx9: Implement D3DXAssembleShader function, really basic shader assembler. Currently it only accepts a minimal subset of the syntax (e.g. just an instruction and two register types supported) and doesn't produce any real output (i.e. shader bytecode).
2010-03-28 21:16:09 +02:00
/* Version tokens */
%token VER_VS10
%token VER_VS11
%token VER_VS20
%token VER_VS2X
%token VER_VS30
%token VER_PS10
%token VER_PS11
%token VER_PS12
%token VER_PS13
%token VER_PS14
%token VER_PS20
%token VER_PS2X
%token VER_PS30
d3dx9: Add instruction modifiers (sm 2.0+) support to the shader assembler.
2010-04-21 16:15:46 +02:00
/* Output modifiers */
d3dx9: Add ps_1_x source register modifiers to the shader assembler.
2010-07-20 15:01:16 +02:00
%token SHIFT_X2
d3dx9: Add shift modifiers parsing to the shader assembler.
2010-07-20 15:01:16 +02:00
%token SHIFT_X4
%token SHIFT_X8
%token SHIFT_D2
%token SHIFT_D4
%token SHIFT_D8
d3dx9: Add instruction modifiers (sm 2.0+) support to the shader assembler.
2010-04-21 16:15:46 +02:00
%token MOD_SAT
%token MOD_PP
%token MOD_CENTROID
d3dx9: Add other flow control instructions in the shader assembler.
2009-11-24 02:08:32 +01:00
/* Compare tokens */
%token COMP_GT
%token COMP_LT
%token COMP_GE
%token COMP_LE
%token COMP_EQ
%token COMP_NE
d3dx9: Add source register modifiers (sm 2+) support to the shader assembler.
2010-04-21 16:15:46 +02:00
/* Source register modifiers */
d3dx9: Add ps_1_x source register modifiers to the shader assembler.
2010-07-20 15:01:16 +02:00
%token SMOD_BIAS
%token SMOD_SCALEBIAS
%token SMOD_DZ
%token SMOD_DW
d3dx9: Add source register modifiers (sm 2+) support to the shader assembler.
2010-04-21 16:15:46 +02:00
%token SMOD_ABS
d3dx9: Support some flow control instructions in the shader assembler.
2010-05-11 20:29:07 +02:00
%token SMOD_NOT
d3dx9: Add source register modifiers (sm 2+) support to the shader assembler.
2010-04-21 16:15:46 +02:00
d3dx9: Add sampler dcl instruction support to the shader assembler.
2010-05-13 17:21:59 +02:00
/* Sampler types */
%token SAMPTYPE_1D
%token SAMPTYPE_2D
%token SAMPTYPE_CUBE
%token SAMPTYPE_VOLUME
d3dx9: Add output dcl instruction partial support to the shader assembler.
2010-05-13 17:21:58 +02:00
/* Usage declaration tokens */
%token <regnum> USAGE_POSITION
d3dx9: Complete output dcl instruction support.
2010-05-13 17:21:58 +02:00
%token <regnum> USAGE_BLENDWEIGHT
%token <regnum> USAGE_BLENDINDICES
%token <regnum> USAGE_NORMAL
%token <regnum> USAGE_PSIZE
%token <regnum> USAGE_TEXCOORD
%token <regnum> USAGE_TANGENT
%token <regnum> USAGE_BINORMAL
%token <regnum> USAGE_TESSFACTOR
%token <regnum> USAGE_POSITIONT
%token <regnum> USAGE_COLOR
%token <regnum> USAGE_FOG
%token <regnum> USAGE_DEPTH
%token <regnum> USAGE_SAMPLE
d3dx9: Add output dcl instruction partial support to the shader assembler.
2010-05-13 17:21:58 +02:00
d3dx9: Add swizzle and writemask support to the shader assembler.
2010-04-21 16:15:46 +02:00
/* Misc stuff */
%token <component> COMPONENT
d3dx9: Add relative addressing support to the shader assembler.
2010-05-05 19:55:26 +02:00
%token <immval> IMMVAL
d3dx9: Add DEFB instruction support in the shader assembler. This completes vs_3_0 assembler language support.
2010-05-14 17:21:42 +02:00
%token <immbool> IMMBOOL
d3dx9: Implement D3DXAssembleShader function, really basic shader assembler. Currently it only accepts a minimal subset of the syntax (e.g. just an instruction and two register types supported) and doesn't produce any real output (i.e. shader bytecode).
2010-03-28 21:16:09 +02:00
%type <reg> dreg_name
%type <reg> dreg
%type <reg> sreg_name
d3dx9: Add relative addressing support to the shader assembler.
2010-05-05 19:55:26 +02:00
%type <reg> relreg_name
d3dx9: Implement D3DXAssembleShader function, really basic shader assembler. Currently it only accepts a minimal subset of the syntax (e.g. just an instruction and two register types supported) and doesn't produce any real output (i.e. shader bytecode).
2010-03-28 21:16:09 +02:00
%type <reg> sreg
d3dx9: Add source register modifiers (sm 2+) support to the shader assembler.
2010-04-21 16:15:46 +02:00
%type <srcmod> smod
d3dx9: Add swizzle and writemask support to the shader assembler.
2010-04-21 16:15:46 +02:00
%type <writemask> writemask
%type <wm_components> wm_components
d3dx9: Implement D3DXAssembleShader function, really basic shader assembler. Currently it only accepts a minimal subset of the syntax (e.g. just an instruction and two register types supported) and doesn't produce any real output (i.e. shader bytecode).
2010-03-28 21:16:09 +02:00
%type <swizzle> swizzle
d3dx9: Add swizzle and writemask support to the shader assembler.
2010-04-21 16:15:46 +02:00
%type <sw_components> sw_components
d3dx9: Implement D3DXAssembleShader function, really basic shader assembler. Currently it only accepts a minimal subset of the syntax (e.g. just an instruction and two register types supported) and doesn't produce any real output (i.e. shader bytecode).
2010-03-28 21:16:09 +02:00
%type <modshift> omods
d3dx9: Add instruction modifiers (sm 2.0+) support to the shader assembler.
2010-04-21 16:15:46 +02:00
%type <modshift> omodifier
d3dx9: Add other flow control instructions in the shader assembler.
2009-11-24 02:08:32 +01:00
%type <comptype> comp
d3dx9: Add output dcl instruction partial support to the shader assembler.
2010-05-13 17:21:58 +02:00
%type <declaration> dclusage
d3dx9: Accept texture coordinate registers in dcl instruction.
2010-06-08 00:53:23 +02:00
%type <reg> dcl_inputreg
d3dx9: Add sampler dcl instruction support to the shader assembler.
2010-05-13 17:21:59 +02:00
%type <samplertype> sampdcl
d3dx9: Implement D3DXAssembleShader function, really basic shader assembler. Currently it only accepts a minimal subset of the syntax (e.g. just an instruction and two register types supported) and doesn't produce any real output (i.e. shader bytecode).
2010-03-28 21:16:09 +02:00
%type <rel_reg> rel_reg
d3dx9: Add predicate support to the shader assembler.
2010-05-11 20:29:07 +02:00
%type <reg> predicate
d3dx9: Add relative addressing support to the shader assembler.
2010-05-05 19:55:26 +02:00
%type <immval> immsum
d3dx9: Implement D3DXAssembleShader function, really basic shader assembler. Currently it only accepts a minimal subset of the syntax (e.g. just an instruction and two register types supported) and doesn't produce any real output (i.e. shader bytecode).
2010-03-28 21:16:09 +02:00
%type <sregs> sregs
%%
shader: version_marker instructions
{
asm_ctx.funcs->end(&asm_ctx);
}
version_marker: VER_VS10
{
TRACE("Vertex shader 1.0\n");
d3dx9: Shader assembler vs_1_0 and vs_1_1 support.
2009-08-16 01:02:16 +02:00
create_vs10_parser(&asm_ctx);
d3dx9: Implement D3DXAssembleShader function, really basic shader assembler. Currently it only accepts a minimal subset of the syntax (e.g. just an instruction and two register types supported) and doesn't produce any real output (i.e. shader bytecode).
2010-03-28 21:16:09 +02:00
}
| VER_VS11
{
TRACE("Vertex shader 1.1\n");
d3dx9: Shader assembler vs_1_0 and vs_1_1 support.
2009-08-16 01:02:16 +02:00
create_vs11_parser(&asm_ctx);
d3dx9: Implement D3DXAssembleShader function, really basic shader assembler. Currently it only accepts a minimal subset of the syntax (e.g. just an instruction and two register types supported) and doesn't produce any real output (i.e. shader bytecode).
2010-03-28 21:16:09 +02:00
}
| VER_VS20
{
TRACE("Vertex shader 2.0\n");
d3dx9: Shader assembler vs_2_x support.
2010-05-16 20:57:52 +02:00
create_vs20_parser(&asm_ctx);
d3dx9: Implement D3DXAssembleShader function, really basic shader assembler. Currently it only accepts a minimal subset of the syntax (e.g. just an instruction and two register types supported) and doesn't produce any real output (i.e. shader bytecode).
2010-03-28 21:16:09 +02:00
}
| VER_VS2X
{
TRACE("Vertex shader 2.x\n");
d3dx9: Shader assembler vs_2_x support.
2010-05-16 20:57:52 +02:00
create_vs2x_parser(&asm_ctx);
d3dx9: Implement D3DXAssembleShader function, really basic shader assembler. Currently it only accepts a minimal subset of the syntax (e.g. just an instruction and two register types supported) and doesn't produce any real output (i.e. shader bytecode).
2010-03-28 21:16:09 +02:00
}
| VER_VS30
{
TRACE("Vertex shader 3.0\n");
create_vs30_parser(&asm_ctx);
}
| VER_PS10
{
TRACE("Pixel shader 1.0\n");
d3dx9: Shader assembler <= ps_1_3 support.
2010-07-21 17:07:24 +02:00
create_ps10_parser(&asm_ctx);
d3dx9: Implement D3DXAssembleShader function, really basic shader assembler. Currently it only accepts a minimal subset of the syntax (e.g. just an instruction and two register types supported) and doesn't produce any real output (i.e. shader bytecode).
2010-03-28 21:16:09 +02:00
}
| VER_PS11
{
TRACE("Pixel shader 1.1\n");
d3dx9: Shader assembler <= ps_1_3 support.
2010-07-21 17:07:24 +02:00
create_ps11_parser(&asm_ctx);
d3dx9: Implement D3DXAssembleShader function, really basic shader assembler. Currently it only accepts a minimal subset of the syntax (e.g. just an instruction and two register types supported) and doesn't produce any real output (i.e. shader bytecode).
2010-03-28 21:16:09 +02:00
}
| VER_PS12
{
TRACE("Pixel shader 1.2\n");
d3dx9: Shader assembler <= ps_1_3 support.
2010-07-21 17:07:24 +02:00
create_ps12_parser(&asm_ctx);
d3dx9: Implement D3DXAssembleShader function, really basic shader assembler. Currently it only accepts a minimal subset of the syntax (e.g. just an instruction and two register types supported) and doesn't produce any real output (i.e. shader bytecode).
2010-03-28 21:16:09 +02:00
}
| VER_PS13
{
TRACE("Pixel shader 1.3\n");
d3dx9: Shader assembler <= ps_1_3 support.
2010-07-21 17:07:24 +02:00
create_ps13_parser(&asm_ctx);
d3dx9: Implement D3DXAssembleShader function, really basic shader assembler. Currently it only accepts a minimal subset of the syntax (e.g. just an instruction and two register types supported) and doesn't produce any real output (i.e. shader bytecode).
2010-03-28 21:16:09 +02:00
}
| VER_PS14
{
TRACE("Pixel shader 1.4\n");
d3dx9: Shader assembler ps_1_4 support.
2010-07-20 15:01:16 +02:00
create_ps14_parser(&asm_ctx);
d3dx9: Implement D3DXAssembleShader function, really basic shader assembler. Currently it only accepts a minimal subset of the syntax (e.g. just an instruction and two register types supported) and doesn't produce any real output (i.e. shader bytecode).
2010-03-28 21:16:09 +02:00
}
| VER_PS20
{
TRACE("Pixel shader 2.0\n");
d3dx9: Shader assembler ps_2_x support.
2010-05-20 01:14:25 +02:00
create_ps20_parser(&asm_ctx);
d3dx9: Implement D3DXAssembleShader function, really basic shader assembler. Currently it only accepts a minimal subset of the syntax (e.g. just an instruction and two register types supported) and doesn't produce any real output (i.e. shader bytecode).
2010-03-28 21:16:09 +02:00
}
| VER_PS2X
{
TRACE("Pixel shader 2.x\n");
d3dx9: Shader assembler ps_2_x support.
2010-05-20 01:14:25 +02:00
create_ps2x_parser(&asm_ctx);
d3dx9: Implement D3DXAssembleShader function, really basic shader assembler. Currently it only accepts a minimal subset of the syntax (e.g. just an instruction and two register types supported) and doesn't produce any real output (i.e. shader bytecode).
2010-03-28 21:16:09 +02:00
}
| VER_PS30
{
TRACE("Pixel shader 3.0\n");
d3dx9: Shader assembler ps_3_0 support.
2010-05-19 14:57:38 +02:00
create_ps30_parser(&asm_ctx);
d3dx9: Implement D3DXAssembleShader function, really basic shader assembler. Currently it only accepts a minimal subset of the syntax (e.g. just an instruction and two register types supported) and doesn't produce any real output (i.e. shader bytecode).
2010-03-28 21:16:09 +02:00
}
instructions: /* empty */
| instructions complexinstr
{
/* Nothing to do */
}
complexinstr: instruction
{
}
d3dx9: Add predicate support to the shader assembler.
2010-05-11 20:29:07 +02:00
| predicate instruction
{
TRACE("predicate\n");
asm_ctx.funcs->predicate(&asm_ctx, &$1);
}
d3dx9: Shader assembler ps_1_4 support.
2010-07-20 15:01:16 +02:00
| '+' instruction
{
TRACE("coissue\n");
asm_ctx.funcs->coissue(&asm_ctx);
}
d3dx9: Implement D3DXAssembleShader function, really basic shader assembler. Currently it only accepts a minimal subset of the syntax (e.g. just an instruction and two register types supported) and doesn't produce any real output (i.e. shader bytecode).
2010-03-28 21:16:09 +02:00
d3dx9: Support some more vs_3_0 instructions in the shader assembler.
2010-05-05 20:21:10 +02:00
instruction: INSTR_ADD omods dreg ',' sregs
{
TRACE("ADD\n");
asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_ADD, $2.mod, $2.shift, 0, &$3, &$5, 2);
}
| INSTR_NOP
{
TRACE("NOP\n");
asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_NOP, 0, 0, 0, 0, 0, 0);
}
| INSTR_MOV omods dreg ',' sregs
d3dx9: Implement D3DXAssembleShader function, really basic shader assembler. Currently it only accepts a minimal subset of the syntax (e.g. just an instruction and two register types supported) and doesn't produce any real output (i.e. shader bytecode).
2010-03-28 21:16:09 +02:00
{
TRACE("MOV\n");
asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_MOV, $2.mod, $2.shift, 0, &$3, &$5, 1);
}
d3dx9: Support some more vs_3_0 instructions in the shader assembler.
2010-05-05 20:21:10 +02:00
| INSTR_SUB omods dreg ',' sregs
{
TRACE("SUB\n");
asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_SUB, $2.mod, $2.shift, 0, &$3, &$5, 2);
}
| INSTR_MAD omods dreg ',' sregs
{
TRACE("MAD\n");
asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_MAD, $2.mod, $2.shift, 0, &$3, &$5, 3);
}
| INSTR_MUL omods dreg ',' sregs
{
TRACE("MUL\n");
asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_MUL, $2.mod, $2.shift, 0, &$3, &$5, 2);
}
| INSTR_RCP omods dreg ',' sregs
{
TRACE("RCP\n");
asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_RCP, $2.mod, $2.shift, 0, &$3, &$5, 1);
}
| INSTR_RSQ omods dreg ',' sregs
{
TRACE("RSQ\n");
asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_RSQ, $2.mod, $2.shift, 0, &$3, &$5, 1);
}
| INSTR_DP3 omods dreg ',' sregs
{
TRACE("DP3\n");
asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_DP3, $2.mod, $2.shift, 0, &$3, &$5, 2);
}
| INSTR_DP4 omods dreg ',' sregs
{
TRACE("DP4\n");
asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_DP4, $2.mod, $2.shift, 0, &$3, &$5, 2);
}
| INSTR_MIN omods dreg ',' sregs
{
TRACE("MIN\n");
asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_MIN, $2.mod, $2.shift, 0, &$3, &$5, 2);
}
| INSTR_MAX omods dreg ',' sregs
{
TRACE("MAX\n");
asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_MAX, $2.mod, $2.shift, 0, &$3, &$5, 2);
}
| INSTR_SLT omods dreg ',' sregs
{
TRACE("SLT\n");
asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_SLT, $2.mod, $2.shift, 0, &$3, &$5, 2);
}
| INSTR_SGE omods dreg ',' sregs
{
TRACE("SGE\n");
asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_SGE, $2.mod, $2.shift, 0, &$3, &$5, 2);
}
| INSTR_ABS omods dreg ',' sregs
{
TRACE("ABS\n");
asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_ABS, $2.mod, $2.shift, 0, &$3, &$5, 1);
}
| INSTR_EXP omods dreg ',' sregs
{
TRACE("EXP\n");
asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_EXP, $2.mod, $2.shift, 0, &$3, &$5, 1);
}
| INSTR_LOG omods dreg ',' sregs
{
TRACE("LOG\n");
asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_LOG, $2.mod, $2.shift, 0, &$3, &$5, 1);
}
| INSTR_LOGP omods dreg ',' sregs
{
TRACE("LOGP\n");
asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_LOGP, $2.mod, $2.shift, 0, &$3, &$5, 1);
}
| INSTR_EXPP omods dreg ',' sregs
{
TRACE("EXPP\n");
asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_EXPP, $2.mod, $2.shift, 0, &$3, &$5, 1);
}
| INSTR_DST omods dreg ',' sregs
{
TRACE("DST\n");
asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_DST, $2.mod, $2.shift, 0, &$3, &$5, 2);
}
| INSTR_LRP omods dreg ',' sregs
{
TRACE("LRP\n");
asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_LRP, $2.mod, $2.shift, 0, &$3, &$5, 3);
}
| INSTR_FRC omods dreg ',' sregs
{
TRACE("FRC\n");
asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_FRC, $2.mod, $2.shift, 0, &$3, &$5, 1);
}
| INSTR_POW omods dreg ',' sregs
{
TRACE("POW\n");
asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_POW, $2.mod, $2.shift, 0, &$3, &$5, 2);
}
| INSTR_CRS omods dreg ',' sregs
{
TRACE("CRS\n");
asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_CRS, $2.mod, $2.shift, 0, &$3, &$5, 2);
}
| INSTR_SGN omods dreg ',' sregs
{
TRACE("SGN\n");
asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_SGN, $2.mod, $2.shift, 0, &$3, &$5, 3);
}
| INSTR_NRM omods dreg ',' sregs
{
TRACE("NRM\n");
asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_NRM, $2.mod, $2.shift, 0, &$3, &$5, 1);
}
| INSTR_SINCOS omods dreg ',' sregs
{
TRACE("SINCOS\n");
asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_SINCOS, $2.mod, $2.shift, 0, &$3, &$5, 1);
}
| INSTR_M4x4 omods dreg ',' sregs
{
TRACE("M4x4\n");
asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_M4x4, $2.mod, $2.shift, 0, &$3, &$5, 2);
}
| INSTR_M4x3 omods dreg ',' sregs
{
TRACE("M4x3\n");
asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_M4x3, $2.mod, $2.shift, 0, &$3, &$5, 2);
}
| INSTR_M3x4 omods dreg ',' sregs
{
TRACE("M3x4\n");
asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_M3x4, $2.mod, $2.shift, 0, &$3, &$5, 2);
}
| INSTR_M3x3 omods dreg ',' sregs
{
TRACE("M3x3\n");
asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_M3x3, $2.mod, $2.shift, 0, &$3, &$5, 2);
}
| INSTR_M3x2 omods dreg ',' sregs
{
TRACE("M3x2\n");
asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_M3x2, $2.mod, $2.shift, 0, &$3, &$5, 2);
}
d3dx9: Add output dcl instruction partial support to the shader assembler.
2010-05-13 17:21:58 +02:00
| INSTR_DCL dclusage REG_OUTPUT
{
struct shader_reg reg;
TRACE("Output reg declaration\n");
ZeroMemory(&reg, sizeof(reg));
reg.type = BWRITERSPR_OUTPUT;
reg.regnum = $3;
reg.rel_reg = NULL;
reg.srcmod = 0;
d3dcompiler_43: Don't use nameless unions in our private structures to avoid trouble with compilers where they are not supported.
2010-08-29 23:40:33 +02:00
reg.u.writemask = BWRITERSP_WRITEMASK_ALL;
d3dx9: Add output dcl instruction partial support to the shader assembler.
2010-05-13 17:21:58 +02:00
asm_ctx.funcs->dcl_output(&asm_ctx, $2.dclusage, $2.regnum, &reg);
}
| INSTR_DCL dclusage REG_OUTPUT writemask
{
struct shader_reg reg;
TRACE("Output reg declaration\n");
ZeroMemory(&reg, sizeof(reg));
reg.type = BWRITERSPR_OUTPUT;
reg.regnum = $3;
reg.rel_reg = NULL;
reg.srcmod = 0;
d3dcompiler_43: Don't use nameless unions in our private structures to avoid trouble with compilers where they are not supported.
2010-08-29 23:40:33 +02:00
reg.u.writemask = $4;
d3dx9: Add output dcl instruction partial support to the shader assembler.
2010-05-13 17:21:58 +02:00
asm_ctx.funcs->dcl_output(&asm_ctx, $2.dclusage, $2.regnum, &reg);
}
d3dx9: Accept texture coordinate registers in dcl instruction.
2010-06-08 00:53:23 +02:00
| INSTR_DCL dclusage omods dcl_inputreg
d3dx9: Add input dcl instruction support to the shader assembler.
2010-05-13 17:21:58 +02:00
{
struct shader_reg reg;
TRACE("Input reg declaration\n");
d3dx9: Allow modifiers on the ps dcl input instruction.
2010-05-30 22:24:54 +02:00
if($3.shift != 0) {
asmparser_message(&asm_ctx, "Line %u: Shift modifier not allowed here\n",
asm_ctx.line_no);
d3dcompiler: Make set_parse_status() more general.
2012-05-08 16:17:30 +02:00
set_parse_status(&asm_ctx.status, PARSE_ERR);
d3dx9: Allow modifiers on the ps dcl input instruction.
2010-05-30 22:24:54 +02:00
}
d3dx9: Check dcl input instruction syntax against shader version.
2010-07-17 21:57:38 +02:00
if(asm_ctx.shader->version == BWRITERPS_VERSION(2, 0) ||
asm_ctx.shader->version == BWRITERPS_VERSION(2, 1)) {
asmparser_message(&asm_ctx, "Line %u: Declaration not supported in PS 2\n",
asm_ctx.line_no);
d3dcompiler: Make set_parse_status() more general.
2012-05-08 16:17:30 +02:00
set_parse_status(&asm_ctx.status, PARSE_ERR);
d3dx9: Check dcl input instruction syntax against shader version.
2010-07-17 21:57:38 +02:00
}
d3dx9: Add input dcl instruction support to the shader assembler.
2010-05-13 17:21:58 +02:00
ZeroMemory(&reg, sizeof(reg));
d3dx9: Accept texture coordinate registers in dcl instruction.
2010-06-08 00:53:23 +02:00
reg.type = $4.type;
reg.regnum = $4.regnum;
d3dx9: Add input dcl instruction support to the shader assembler.
2010-05-13 17:21:58 +02:00
reg.rel_reg = NULL;
reg.srcmod = 0;
d3dcompiler_43: Don't use nameless unions in our private structures to avoid trouble with compilers where they are not supported.
2010-08-29 23:40:33 +02:00
reg.u.writemask = BWRITERSP_WRITEMASK_ALL;
d3dx9: Allow modifiers on the ps dcl input instruction.
2010-05-30 22:24:54 +02:00
asm_ctx.funcs->dcl_input(&asm_ctx, $2.dclusage, $2.regnum, $3.mod, &reg);
d3dx9: Add input dcl instruction support to the shader assembler.
2010-05-13 17:21:58 +02:00
}
d3dx9: Accept texture coordinate registers in dcl instruction.
2010-06-08 00:53:23 +02:00
| INSTR_DCL dclusage omods dcl_inputreg writemask
d3dx9: Add input dcl instruction support to the shader assembler.
2010-05-13 17:21:58 +02:00
{
struct shader_reg reg;
TRACE("Input reg declaration\n");
d3dx9: Allow modifiers on the ps dcl input instruction.
2010-05-30 22:24:54 +02:00
if($3.shift != 0) {
asmparser_message(&asm_ctx, "Line %u: Shift modifier not allowed here\n",
asm_ctx.line_no);
d3dcompiler: Make set_parse_status() more general.
2012-05-08 16:17:30 +02:00
set_parse_status(&asm_ctx.status, PARSE_ERR);
d3dx9: Allow modifiers on the ps dcl input instruction.
2010-05-30 22:24:54 +02:00
}
d3dx9: Check dcl input instruction syntax against shader version.
2010-07-17 21:57:38 +02:00
if(asm_ctx.shader->version == BWRITERPS_VERSION(2, 0) ||
asm_ctx.shader->version == BWRITERPS_VERSION(2, 1)) {
asmparser_message(&asm_ctx, "Line %u: Declaration not supported in PS 2\n",
asm_ctx.line_no);
d3dcompiler: Make set_parse_status() more general.
2012-05-08 16:17:30 +02:00
set_parse_status(&asm_ctx.status, PARSE_ERR);
d3dx9: Check dcl input instruction syntax against shader version.
2010-07-17 21:57:38 +02:00
}
d3dx9: Add input dcl instruction support to the shader assembler.
2010-05-13 17:21:58 +02:00
ZeroMemory(&reg, sizeof(reg));
d3dx9: Accept texture coordinate registers in dcl instruction.
2010-06-08 00:53:23 +02:00
reg.type = $4.type;
reg.regnum = $4.regnum;
d3dx9: Add input dcl instruction support to the shader assembler.
2010-05-13 17:21:58 +02:00
reg.rel_reg = NULL;
reg.srcmod = 0;
d3dcompiler_43: Don't use nameless unions in our private structures to avoid trouble with compilers where they are not supported.
2010-08-29 23:40:33 +02:00
reg.u.writemask = $5;
d3dx9: Allow modifiers on the ps dcl input instruction.
2010-05-30 22:24:54 +02:00
asm_ctx.funcs->dcl_input(&asm_ctx, $2.dclusage, $2.regnum, $3.mod, &reg);
d3dx9: Add input dcl instruction support to the shader assembler.
2010-05-13 17:21:58 +02:00
}
d3dx9: Accept texture coordinate registers in dcl instruction.
2010-06-08 00:53:23 +02:00
| INSTR_DCL omods dcl_inputreg
d3dx9: Support ps_2_0-style dcl instruction in the shader assembler.
2010-06-08 00:50:57 +02:00
{
struct shader_reg reg;
TRACE("Input reg declaration\n");
if($2.shift != 0) {
asmparser_message(&asm_ctx, "Line %u: Shift modifier not allowed here\n",
asm_ctx.line_no);
d3dcompiler: Make set_parse_status() more general.
2012-05-08 16:17:30 +02:00
set_parse_status(&asm_ctx.status, PARSE_ERR);
d3dx9: Support ps_2_0-style dcl instruction in the shader assembler.
2010-06-08 00:50:57 +02:00
}
d3dx9: Check dcl input instruction syntax against shader version.
2010-07-17 21:57:38 +02:00
if(asm_ctx.shader->type != ST_PIXEL) {
asmparser_message(&asm_ctx, "Line %u: Declaration needs a semantic\n",
asm_ctx.line_no);
d3dcompiler: Make set_parse_status() more general.
2012-05-08 16:17:30 +02:00
set_parse_status(&asm_ctx.status, PARSE_ERR);
d3dx9: Check dcl input instruction syntax against shader version.
2010-07-17 21:57:38 +02:00
}
d3dx9: Support ps_2_0-style dcl instruction in the shader assembler.
2010-06-08 00:50:57 +02:00
ZeroMemory(&reg, sizeof(reg));
d3dx9: Accept texture coordinate registers in dcl instruction.
2010-06-08 00:53:23 +02:00
reg.type = $3.type;
reg.regnum = $3.regnum;
d3dx9: Support ps_2_0-style dcl instruction in the shader assembler.
2010-06-08 00:50:57 +02:00
reg.rel_reg = NULL;
reg.srcmod = 0;
d3dcompiler_43: Don't use nameless unions in our private structures to avoid trouble with compilers where they are not supported.
2010-08-29 23:40:33 +02:00
reg.u.writemask = BWRITERSP_WRITEMASK_ALL;
d3dx9: Support ps_2_0-style dcl instruction in the shader assembler.
2010-06-08 00:50:57 +02:00
asm_ctx.funcs->dcl_input(&asm_ctx, 0, 0, $2.mod, &reg);
}
d3dx9: Accept texture coordinate registers in dcl instruction.
2010-06-08 00:53:23 +02:00
| INSTR_DCL omods dcl_inputreg writemask
d3dx9: Support ps_2_0-style dcl instruction in the shader assembler.
2010-06-08 00:50:57 +02:00
{
struct shader_reg reg;
TRACE("Input reg declaration\n");
if($2.shift != 0) {
asmparser_message(&asm_ctx, "Line %u: Shift modifier not allowed here\n",
asm_ctx.line_no);
d3dcompiler: Make set_parse_status() more general.
2012-05-08 16:17:30 +02:00
set_parse_status(&asm_ctx.status, PARSE_ERR);
d3dx9: Support ps_2_0-style dcl instruction in the shader assembler.
2010-06-08 00:50:57 +02:00
}
d3dx9: Check dcl input instruction syntax against shader version.
2010-07-17 21:57:38 +02:00
if(asm_ctx.shader->type != ST_PIXEL) {
asmparser_message(&asm_ctx, "Line %u: Declaration needs a semantic\n",
asm_ctx.line_no);
d3dcompiler: Make set_parse_status() more general.
2012-05-08 16:17:30 +02:00
set_parse_status(&asm_ctx.status, PARSE_ERR);
d3dx9: Check dcl input instruction syntax against shader version.
2010-07-17 21:57:38 +02:00
}
d3dx9: Support ps_2_0-style dcl instruction in the shader assembler.
2010-06-08 00:50:57 +02:00
ZeroMemory(&reg, sizeof(reg));
d3dx9: Accept texture coordinate registers in dcl instruction.
2010-06-08 00:53:23 +02:00
reg.type = $3.type;
reg.regnum = $3.regnum;
d3dx9: Support ps_2_0-style dcl instruction in the shader assembler.
2010-06-08 00:50:57 +02:00
reg.rel_reg = NULL;
reg.srcmod = 0;
d3dcompiler_43: Don't use nameless unions in our private structures to avoid trouble with compilers where they are not supported.
2010-08-29 23:40:33 +02:00
reg.u.writemask = $4;
d3dx9: Support ps_2_0-style dcl instruction in the shader assembler.
2010-06-08 00:50:57 +02:00
asm_ctx.funcs->dcl_input(&asm_ctx, 0, 0, $2.mod, &reg);
}
d3dx9: Allow modifiers on the ps dcl sampler instruction.
2010-05-30 22:57:13 +02:00
| INSTR_DCL sampdcl omods REG_SAMPLER
d3dx9: Add sampler dcl instruction support to the shader assembler.
2010-05-13 17:21:59 +02:00
{
TRACE("Sampler declared\n");
d3dx9: Allow modifiers on the ps dcl sampler instruction.
2010-05-30 22:57:13 +02:00
if($3.shift != 0) {
asmparser_message(&asm_ctx, "Line %u: Shift modifier not allowed here\n",
asm_ctx.line_no);
d3dcompiler: Make set_parse_status() more general.
2012-05-08 16:17:30 +02:00
set_parse_status(&asm_ctx.status, PARSE_ERR);
d3dx9: Allow modifiers on the ps dcl sampler instruction.
2010-05-30 22:57:13 +02:00
}
asm_ctx.funcs->dcl_sampler(&asm_ctx, $2, $3.mod, $4, asm_ctx.line_no);
d3dx9: Add sampler dcl instruction support to the shader assembler.
2010-05-13 17:21:59 +02:00
}
d3dx9: Allow sampler declaration without sampler type.
2010-06-08 03:20:20 +02:00
| INSTR_DCL omods REG_SAMPLER
{
TRACE("Sampler declared\n");
if($2.shift != 0) {
asmparser_message(&asm_ctx, "Line %u: Shift modifier not allowed here\n",
asm_ctx.line_no);
d3dcompiler: Make set_parse_status() more general.
2012-05-08 16:17:30 +02:00
set_parse_status(&asm_ctx.status, PARSE_ERR);
d3dx9: Allow sampler declaration without sampler type.
2010-06-08 03:20:20 +02:00
}
if(asm_ctx.shader->type != ST_PIXEL) {
asmparser_message(&asm_ctx, "Line %u: Declaration needs a sampler type\n",
asm_ctx.line_no);
d3dcompiler: Make set_parse_status() more general.
2012-05-08 16:17:30 +02:00
set_parse_status(&asm_ctx.status, PARSE_ERR);
d3dx9: Allow sampler declaration without sampler type.
2010-06-08 03:20:20 +02:00
}
asm_ctx.funcs->dcl_sampler(&asm_ctx, BWRITERSTT_UNKNOWN, $2.mod, $3, asm_ctx.line_no);
}
d3dx9: Accept texture coordinate registers in dcl instruction.
2010-06-08 00:53:23 +02:00
| INSTR_DCL sampdcl omods dcl_inputreg
d3dx9: Add sampler dcl instruction support to the shader assembler.
2010-05-13 17:21:59 +02:00
{
TRACE("Error rule: sampler decl of input reg\n");
asmparser_message(&asm_ctx, "Line %u: Sampler declarations of input regs is not valid\n",
asm_ctx.line_no);
d3dcompiler: Make set_parse_status() more general.
2012-05-08 16:17:30 +02:00
set_parse_status(&asm_ctx.status, PARSE_WARN);
d3dx9: Add sampler dcl instruction support to the shader assembler.
2010-05-13 17:21:59 +02:00
}
d3dx9: Allow modifiers on the ps dcl sampler instruction.
2010-05-30 22:57:13 +02:00
| INSTR_DCL sampdcl omods REG_OUTPUT
d3dx9: Add sampler dcl instruction support to the shader assembler.
2010-05-13 17:21:59 +02:00
{
TRACE("Error rule: sampler decl of output reg\n");
asmparser_message(&asm_ctx, "Line %u: Sampler declarations of output regs is not valid\n",
asm_ctx.line_no);
d3dcompiler: Make set_parse_status() more general.
2012-05-08 16:17:30 +02:00
set_parse_status(&asm_ctx.status, PARSE_WARN);
d3dx9: Add sampler dcl instruction support to the shader assembler.
2010-05-13 17:21:59 +02:00
}
d3dx9: Add DEF instruction support in the shader assembler.
2010-05-14 17:21:42 +02:00
| INSTR_DEF REG_CONSTFLOAT ',' IMMVAL ',' IMMVAL ',' IMMVAL ',' IMMVAL
{
asm_ctx.funcs->constF(&asm_ctx, $2, $4.val, $6.val, $8.val, $10.val);
d3dx9: Add DEFI instruction support in the shader assembler.
2010-05-14 17:21:42 +02:00
}
| INSTR_DEFI REG_CONSTINT ',' IMMVAL ',' IMMVAL ',' IMMVAL ',' IMMVAL
{
asm_ctx.funcs->constI(&asm_ctx, $2, $4.val, $6.val, $8.val, $10.val);
d3dx9: Add DEF instruction support in the shader assembler.
2010-05-14 17:21:42 +02:00
}
d3dx9: Add DEFB instruction support in the shader assembler. This completes vs_3_0 assembler language support.
2010-05-14 17:21:42 +02:00
| INSTR_DEFB REG_CONSTBOOL ',' IMMBOOL
{
asm_ctx.funcs->constB(&asm_ctx, $2, $4);
}
d3dx9: Support some flow control instructions in the shader assembler.
2010-05-11 20:29:07 +02:00
| INSTR_REP sregs
{
TRACE("REP\n");
asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_REP, 0, 0, 0, 0, &$2, 1);
}
| INSTR_ENDREP
{
TRACE("ENDREP\n");
asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_ENDREP, 0, 0, 0, 0, 0, 0);
}
| INSTR_IF sregs
{
TRACE("IF\n");
asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_IF, 0, 0, 0, 0, &$2, 1);
}
d3dx9: Add other flow control instructions in the shader assembler.
2009-11-24 02:08:32 +01:00
| INSTR_IF comp sregs
{
TRACE("IFC\n");
asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_IFC, 0, 0, $2, 0, &$3, 2);
}
d3dx9: Support some flow control instructions in the shader assembler.
2010-05-11 20:29:07 +02:00
| INSTR_ELSE
{
TRACE("ELSE\n");
asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_ELSE, 0, 0, 0, 0, 0, 0);
}
| INSTR_ENDIF
{
TRACE("ENDIF\n");
asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_ENDIF, 0, 0, 0, 0, 0, 0);
}
| INSTR_BREAK
{
TRACE("BREAK\n");
asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_BREAK, 0, 0, 0, 0, 0, 0);
}
d3dx9: Add other flow control instructions in the shader assembler.
2009-11-24 02:08:32 +01:00
| INSTR_BREAK comp sregs
{
TRACE("BREAKC\n");
asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_BREAKC, 0, 0, $2, 0, &$3, 2);
}
d3dx9: Add predicate support to the shader assembler.
2010-05-11 20:29:07 +02:00
| INSTR_BREAKP sregs
{
TRACE("BREAKP\n");
asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_BREAKP, 0, 0, 0, 0, &$2, 1);
}
d3dx9: Support some flow control instructions in the shader assembler.
2010-05-11 20:29:07 +02:00
| INSTR_CALL sregs
{
TRACE("CALL\n");
asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_CALL, 0, 0, 0, 0, &$2, 1);
}
| INSTR_CALLNZ sregs
{
TRACE("CALLNZ\n");
asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_CALLNZ, 0, 0, 0, 0, &$2, 2);
}
| INSTR_LOOP sregs
{
TRACE("LOOP\n");
asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_LOOP, 0, 0, 0, 0, &$2, 2);
}
| INSTR_RET
{
TRACE("RET\n");
asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_RET, 0, 0, 0, 0, 0, 0);
}
| INSTR_ENDLOOP
{
TRACE("ENDLOOP\n");
asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_ENDLOOP, 0, 0, 0, 0, 0, 0);
}
| INSTR_LABEL sregs
{
TRACE("LABEL\n");
asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_LABEL, 0, 0, 0, 0, &$2, 1);
}
d3dx9: Add predicate support to the shader assembler.
2010-05-11 20:29:07 +02:00
| INSTR_SETP comp dreg ',' sregs
{
TRACE("SETP\n");
asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_SETP, 0, 0, $2, &$3, &$5, 2);
}
d3dx9: Support some more vs_3_0 instructions in the shader assembler.
2010-05-05 20:21:10 +02:00
| INSTR_TEXLDL omods dreg ',' sregs
{
TRACE("TEXLDL\n");
asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_TEXLDL, $2.mod, $2.shift, 0, &$3, &$5, 2);
}
| INSTR_LIT omods dreg ',' sregs
{
TRACE("LIT\n");
asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_LIT, $2.mod, $2.shift, 0, &$3, &$5, 1);
}
| INSTR_MOVA omods dreg ',' sregs
{
TRACE("MOVA\n");
asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_MOVA, $2.mod, $2.shift, 0, &$3, &$5, 1);
}
d3dx9: Add ps_1_4 instructions parsing to the shader assembler.
2010-07-20 15:01:16 +02:00
| INSTR_CND omods dreg ',' sregs
{
TRACE("CND\n");
asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_CND, $2.mod, $2.shift, 0, &$3, &$5, 3);
}
d3dx9: Add ps_3_0 instructions parsing to the shader assembler.
2010-05-19 14:57:38 +02:00
| INSTR_CMP omods dreg ',' sregs
{
TRACE("CMP\n");
asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_CMP, $2.mod, $2.shift, 0, &$3, &$5, 3);
}
| INSTR_DP2ADD omods dreg ',' sregs
{
TRACE("DP2ADD\n");
asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_DP2ADD, $2.mod, $2.shift, 0, &$3, &$5, 3);
}
d3dx9: Add <= ps_1_3 instruction parsing to the shader assembler.
2010-07-21 17:07:24 +02:00
| INSTR_TEXCOORD omods dreg
{
TRACE("TEXCOORD\n");
asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_TEXCOORD, $2.mod, $2.shift, 0, &$3, 0, 0);
}
d3dx9: Add ps_1_4 instructions parsing to the shader assembler.
2010-07-20 15:01:16 +02:00
| INSTR_TEXCRD omods dreg ',' sregs
{
TRACE("TEXCRD\n");
/* texcoord and texcrd share the same opcode */
asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_TEXCOORD, $2.mod, $2.shift, 0, &$3, &$5, 1);
}
d3dx9: Add missing texkill instruction parsing.
2010-05-20 01:21:40 +02:00
| INSTR_TEXKILL dreg
{
TRACE("TEXKILL\n");
asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_TEXKILL, 0, 0, 0, &$2, 0, 0);
}
d3dx9: Add <= ps_1_3 instruction parsing to the shader assembler.
2010-07-21 17:07:24 +02:00
| INSTR_TEX omods dreg
{
TRACE("TEX\n");
asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_TEX, $2.mod, $2.shift, 0, &$3, 0, 0);
}
d3dx9: Add ps_1_4 instructions parsing to the shader assembler.
2010-07-20 15:01:16 +02:00
| INSTR_TEXDEPTH omods dreg
{
TRACE("TEXDEPTH\n");
asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_TEXDEPTH, $2.mod, $2.shift, 0, &$3, 0, 0);
}
d3dx9: Add ps_3_0 instructions parsing to the shader assembler.
2010-05-19 14:57:38 +02:00
| INSTR_TEXLD omods dreg ',' sregs
{
TRACE("TEXLD\n");
/* There is more than one acceptable syntax for texld:
with 1 sreg (PS 1.4) or
with 2 sregs (PS 2.0+)
Moreover, texld shares the same opcode as the tex instruction,
so there are a total of 3 valid syntaxes
These variations are handled in asmparser.c */
asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_TEX, $2.mod, $2.shift, 0, &$3, &$5, 2);
}
| INSTR_TEXLDP omods dreg ',' sregs
{
TRACE("TEXLDP\n");
d3dx9: Use separate opcodes for TEXLDP and TEXLDB. There is no reason we have to strictly follow D3D bytecode format in our intermediate representation.
2010-05-21 14:56:43 +02:00
asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_TEXLDP, $2.mod, $2.shift, 0, &$3, &$5, 2);
d3dx9: Add ps_3_0 instructions parsing to the shader assembler.
2010-05-19 14:57:38 +02:00
}
| INSTR_TEXLDB omods dreg ',' sregs
{
TRACE("TEXLDB\n");
d3dx9: Use separate opcodes for TEXLDP and TEXLDB. There is no reason we have to strictly follow D3D bytecode format in our intermediate representation.
2010-05-21 14:56:43 +02:00
asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_TEXLDB, $2.mod, $2.shift, 0, &$3, &$5, 2);
d3dx9: Add ps_3_0 instructions parsing to the shader assembler.
2010-05-19 14:57:38 +02:00
}
d3dx9: Add <= ps_1_3 instruction parsing to the shader assembler.
2010-07-21 17:07:24 +02:00
| INSTR_TEXBEM omods dreg ',' sregs
{
TRACE("TEXBEM\n");
asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_TEXBEM, $2.mod, $2.shift, 0, &$3, &$5, 1);
}
| INSTR_TEXBEML omods dreg ',' sregs
{
TRACE("TEXBEML\n");
asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_TEXBEML, $2.mod, $2.shift, 0, &$3, &$5, 1);
}
| INSTR_TEXREG2AR omods dreg ',' sregs
{
TRACE("TEXREG2AR\n");
asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_TEXREG2AR, $2.mod, $2.shift, 0, &$3, &$5, 1);
}
| INSTR_TEXREG2GB omods dreg ',' sregs
{
TRACE("TEXREG2GB\n");
asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_TEXREG2GB, $2.mod, $2.shift, 0, &$3, &$5, 1);
}
| INSTR_TEXREG2RGB omods dreg ',' sregs
{
TRACE("TEXREG2RGB\n");
asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_TEXREG2RGB, $2.mod, $2.shift, 0, &$3, &$5, 1);
}
| INSTR_TEXM3x2PAD omods dreg ',' sregs
{
TRACE("TEXM3x2PAD\n");
asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_TEXM3x2PAD, $2.mod, $2.shift, 0, &$3, &$5, 1);
}
| INSTR_TEXM3x3PAD omods dreg ',' sregs
{
TRACE("INSTR_TEXM3x3PAD\n");
asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_TEXM3x3PAD, $2.mod, $2.shift, 0, &$3, &$5, 1);
}
| INSTR_TEXM3x3SPEC omods dreg ',' sregs
{
TRACE("TEXM3x3SPEC\n");
asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_TEXM3x3SPEC, $2.mod, $2.shift, 0, &$3, &$5, 2);
}
| INSTR_TEXM3x3VSPEC omods dreg ',' sregs
{
TRACE("TEXM3x3VSPEC\n");
asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_TEXM3x3VSPEC, $2.mod, $2.shift, 0, &$3, &$5, 1);
}
| INSTR_TEXM3x3TEX omods dreg ',' sregs
{
TRACE("TEXM3x3TEX\n");
asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_TEXM3x3TEX, $2.mod, $2.shift, 0, &$3, &$5, 1);
}
| INSTR_TEXDP3TEX omods dreg ',' sregs
{
TRACE("TEXDP3TEX\n");
asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_TEXDP3TEX, $2.mod, $2.shift, 0, &$3, &$5, 1);
}
| INSTR_TEXM3x2DEPTH omods dreg ',' sregs
{
TRACE("TEXM3x2DEPTH\n");
asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_TEXM3x2DEPTH, $2.mod, $2.shift, 0, &$3, &$5, 1);
}
| INSTR_TEXM3x2TEX omods dreg ',' sregs
{
TRACE("TEXM3x2TEX\n");
asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_TEXM3x2TEX, $2.mod, $2.shift, 0, &$3, &$5, 1);
}
| INSTR_TEXDP3 omods dreg ',' sregs
{
TRACE("TEXDP3\n");
asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_TEXDP3, $2.mod, $2.shift, 0, &$3, &$5, 1);
}
| INSTR_TEXM3x3 omods dreg ',' sregs
{
TRACE("TEXM3x3\n");
asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_TEXM3x3, $2.mod, $2.shift, 0, &$3, &$5, 1);
}
d3dx9: Add ps_1_4 instructions parsing to the shader assembler.
2010-07-20 15:01:16 +02:00
| INSTR_BEM omods dreg ',' sregs
{
TRACE("BEM\n");
asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_BEM, $2.mod, $2.shift, 0, &$3, &$5, 2);
}
d3dx9: Add ps_3_0 instructions parsing to the shader assembler.
2010-05-19 14:57:38 +02:00
| INSTR_DSX omods dreg ',' sregs
{
TRACE("DSX\n");
asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_DSX, $2.mod, $2.shift, 0, &$3, &$5, 1);
}
| INSTR_DSY omods dreg ',' sregs
{
TRACE("DSY\n");
asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_DSY, $2.mod, $2.shift, 0, &$3, &$5, 1);
}
| INSTR_TEXLDD omods dreg ',' sregs
{
TRACE("TEXLDD\n");
asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_TEXLDD, $2.mod, $2.shift, 0, &$3, &$5, 4);
}
d3dx9: Add ps_1_4 instructions parsing to the shader assembler.
2010-07-20 15:01:16 +02:00
| INSTR_PHASE
{
TRACE("PHASE\n");
asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_PHASE, 0, 0, 0, 0, 0, 0);
}
d3dx9: Implement D3DXAssembleShader function, really basic shader assembler. Currently it only accepts a minimal subset of the syntax (e.g. just an instruction and two register types supported) and doesn't produce any real output (i.e. shader bytecode).
2010-03-28 21:16:09 +02:00
dreg: dreg_name rel_reg
{
$$.regnum = $1.regnum;
$$.type = $1.type;
d3dcompiler_43: Don't use nameless unions in our private structures to avoid trouble with compilers where they are not supported.
2010-08-29 23:40:33 +02:00
$$.u.writemask = BWRITERSP_WRITEMASK_ALL;
d3dx9: Implement D3DXAssembleShader function, really basic shader assembler. Currently it only accepts a minimal subset of the syntax (e.g. just an instruction and two register types supported) and doesn't produce any real output (i.e. shader bytecode).
2010-03-28 21:16:09 +02:00
$$.srcmod = BWRITERSPSM_NONE;
set_rel_reg(&$$, &$2);
}
d3dx9: Add swizzle and writemask support to the shader assembler.
2010-04-21 16:15:46 +02:00
| dreg_name writemask
{
$$.regnum = $1.regnum;
$$.type = $1.type;
d3dcompiler_43: Don't use nameless unions in our private structures to avoid trouble with compilers where they are not supported.
2010-08-29 23:40:33 +02:00
$$.u.writemask = $2;
d3dx9: Add swizzle and writemask support to the shader assembler.
2010-04-21 16:15:46 +02:00
$$.srcmod = BWRITERSPSM_NONE;
$$.rel_reg = NULL;
}
d3dx9: Implement D3DXAssembleShader function, really basic shader assembler. Currently it only accepts a minimal subset of the syntax (e.g. just an instruction and two register types supported) and doesn't produce any real output (i.e. shader bytecode).
2010-03-28 21:16:09 +02:00
dreg_name: REG_TEMP
{
$$.regnum = $1; $$.type = BWRITERSPR_TEMP;
}
d3dx9: Support all the remaining register types in the shader assembler.
2010-05-05 16:56:09 +02:00
| REG_OUTPUT
{
$$.regnum = $1; $$.type = BWRITERSPR_OUTPUT;
}
| REG_INPUT
{
d3dx9: Add missing texkill instruction parsing.
2010-05-20 01:21:40 +02:00
$$.regnum = $1; $$.type = BWRITERSPR_INPUT;
d3dx9: Support all the remaining register types in the shader assembler.
2010-05-05 16:56:09 +02:00
}
| REG_CONSTFLOAT
{
asmparser_message(&asm_ctx, "Line %u: Register c%u is not a valid destination register\n",
asm_ctx.line_no, $1);
d3dcompiler: Make set_parse_status() more general.
2012-05-08 16:17:30 +02:00
set_parse_status(&asm_ctx.status, PARSE_WARN);
d3dx9: Support all the remaining register types in the shader assembler.
2010-05-05 16:56:09 +02:00
}
| REG_CONSTINT
{
d3dcompiler: Remove some stray tabs.
2010-10-15 14:35:15 +02:00
asmparser_message(&asm_ctx, "Line %u: Register i%u is not a valid destination register\n",
d3dx9: Support all the remaining register types in the shader assembler.
2010-05-05 16:56:09 +02:00
asm_ctx.line_no, $1);
d3dcompiler: Make set_parse_status() more general.
2012-05-08 16:17:30 +02:00
set_parse_status(&asm_ctx.status, PARSE_WARN);
d3dx9: Support all the remaining register types in the shader assembler.
2010-05-05 16:56:09 +02:00
}
| REG_CONSTBOOL
{
asmparser_message(&asm_ctx, "Line %u: Register b%u is not a valid destination register\n",
asm_ctx.line_no, $1);
d3dcompiler: Make set_parse_status() more general.
2012-05-08 16:17:30 +02:00
set_parse_status(&asm_ctx.status, PARSE_WARN);
d3dx9: Support all the remaining register types in the shader assembler.
2010-05-05 16:56:09 +02:00
}
| REG_TEXTURE
{
$$.regnum = $1; $$.type = BWRITERSPR_TEXTURE;
}
| REG_TEXCRDOUT
{
$$.regnum = $1; $$.type = BWRITERSPR_TEXCRDOUT;
}
| REG_SAMPLER
{
asmparser_message(&asm_ctx, "Line %u: Register s%u is not a valid destination register\n",
asm_ctx.line_no, $1);
d3dcompiler: Make set_parse_status() more general.
2012-05-08 16:17:30 +02:00
set_parse_status(&asm_ctx.status, PARSE_WARN);
d3dx9: Support all the remaining register types in the shader assembler.
2010-05-05 16:56:09 +02:00
}
| REG_OPOS
{
$$.regnum = BWRITERSRO_POSITION; $$.type = BWRITERSPR_RASTOUT;
}
| REG_OPTS
{
$$.regnum = BWRITERSRO_POINT_SIZE; $$.type = BWRITERSPR_RASTOUT;
}
| REG_OFOG
{
$$.regnum = BWRITERSRO_FOG; $$.type = BWRITERSPR_RASTOUT;
}
| REG_VERTEXCOLOR
{
$$.regnum = $1; $$.type = BWRITERSPR_ATTROUT;
}
| REG_FRAGCOLOR
{
$$.regnum = $1; $$.type = BWRITERSPR_COLOROUT;
}
| REG_FRAGDEPTH
{
$$.regnum = 0; $$.type = BWRITERSPR_DEPTHOUT;
}
| REG_PREDICATE
{
$$.regnum = 0; $$.type = BWRITERSPR_PREDICATE;
}
| REG_VPOS
{
asmparser_message(&asm_ctx, "Line %u: Register vPos is not a valid destination register\n",
asm_ctx.line_no);
d3dcompiler: Make set_parse_status() more general.
2012-05-08 16:17:30 +02:00
set_parse_status(&asm_ctx.status, PARSE_WARN);
d3dx9: Support all the remaining register types in the shader assembler.
2010-05-05 16:56:09 +02:00
}
| REG_VFACE
{
asmparser_message(&asm_ctx, "Line %u: Register vFace is not a valid destination register\n",
asm_ctx.line_no);
d3dcompiler: Make set_parse_status() more general.
2012-05-08 16:17:30 +02:00
set_parse_status(&asm_ctx.status, PARSE_WARN);
d3dx9: Support all the remaining register types in the shader assembler.
2010-05-05 16:56:09 +02:00
}
| REG_ADDRESS
{
/* index 0 is hardcoded for the addr register */
$$.regnum = 0; $$.type = BWRITERSPR_ADDR;
}
| REG_LOOP
{
asmparser_message(&asm_ctx, "Line %u: Register aL is not a valid destination register\n",
asm_ctx.line_no);
d3dcompiler: Make set_parse_status() more general.
2012-05-08 16:17:30 +02:00
set_parse_status(&asm_ctx.status, PARSE_WARN);
d3dx9: Support all the remaining register types in the shader assembler.
2010-05-05 16:56:09 +02:00
}
d3dx9: Implement D3DXAssembleShader function, really basic shader assembler. Currently it only accepts a minimal subset of the syntax (e.g. just an instruction and two register types supported) and doesn't produce any real output (i.e. shader bytecode).
2010-03-28 21:16:09 +02:00
d3dx9: Add swizzle and writemask support to the shader assembler.
2010-04-21 16:15:46 +02:00
writemask: '.' wm_components
{
if($2.writemask == SWIZZLE_ERR) {
asmparser_message(&asm_ctx, "Line %u: Invalid writemask specified\n",
asm_ctx.line_no);
d3dcompiler: Make set_parse_status() more general.
2012-05-08 16:17:30 +02:00
set_parse_status(&asm_ctx.status, PARSE_ERR);
d3dx9: Add swizzle and writemask support to the shader assembler.
2010-04-21 16:15:46 +02:00
/* Provide a correct writemask to prevent following complaints */
$$ = BWRITERSP_WRITEMASK_ALL;
}
else {
$$ = $2.writemask;
TRACE("Writemask: %x\n", $$);
}
}
wm_components: COMPONENT
{
$$.writemask = 1 << $1;
$$.last = $1;
$$.idx = 1;
}
| wm_components COMPONENT
{
if($1.writemask == SWIZZLE_ERR || $1.idx == 4)
/* Wrong writemask */
$$.writemask = SWIZZLE_ERR;
else {
if($2 <= $1.last)
$$.writemask = SWIZZLE_ERR;
else {
$$.writemask = $1.writemask | (1 << $2);
$$.idx = $1.idx + 1;
}
}
}
d3dx9: Implement D3DXAssembleShader function, really basic shader assembler. Currently it only accepts a minimal subset of the syntax (e.g. just an instruction and two register types supported) and doesn't produce any real output (i.e. shader bytecode).
2010-03-28 21:16:09 +02:00
swizzle: /* empty */
{
$$ = BWRITERVS_NOSWIZZLE;
TRACE("Default swizzle: %08x\n", $$);
}
d3dx9: Add swizzle and writemask support to the shader assembler.
2010-04-21 16:15:46 +02:00
| '.' sw_components
{
if($2.swizzle == SWIZZLE_ERR) {
asmparser_message(&asm_ctx, "Line %u: Invalid swizzle\n",
asm_ctx.line_no);
d3dcompiler: Make set_parse_status() more general.
2012-05-08 16:17:30 +02:00
set_parse_status(&asm_ctx.status, PARSE_ERR);
d3dx9: Add swizzle and writemask support to the shader assembler.
2010-04-21 16:15:46 +02:00
/* Provide a correct swizzle to prevent following complaints */
$$ = BWRITERVS_NOSWIZZLE;
}
else {
DWORD last, i;
$$ = $2.swizzle << BWRITERVS_SWIZZLE_SHIFT;
/* Fill the swizzle by extending the last component */
last = ($2.swizzle >> 2 * ($2.idx - 1)) & 0x03;
for(i = $2.idx; i < 4; i++){
$$ |= last << (BWRITERVS_SWIZZLE_SHIFT + 2 * i);
}
TRACE("Got a swizzle: %08x\n", $$);
}
}
sw_components: COMPONENT
{
$$.swizzle = $1;
$$.idx = 1;
}
| sw_components COMPONENT
{
if($1.idx == 4) {
/* Too many sw_components */
$$.swizzle = SWIZZLE_ERR;
$$.idx = 4;
}
else {
$$.swizzle = $1.swizzle | ($2 << 2 * $1.idx);
$$.idx = $1.idx + 1;
}
}
d3dx9: Implement D3DXAssembleShader function, really basic shader assembler. Currently it only accepts a minimal subset of the syntax (e.g. just an instruction and two register types supported) and doesn't produce any real output (i.e. shader bytecode).
2010-03-28 21:16:09 +02:00
omods: /* Empty */
{
$$.mod = 0;
$$.shift = 0;
}
d3dx9: Add instruction modifiers (sm 2.0+) support to the shader assembler.
2010-04-21 16:15:46 +02:00
| omods omodifier
{
$$.mod = $1.mod | $2.mod;
if($1.shift && $2.shift) {
asmparser_message(&asm_ctx, "Line %u: More than one shift flag\n",
asm_ctx.line_no);
d3dcompiler: Make set_parse_status() more general.
2012-05-08 16:17:30 +02:00
set_parse_status(&asm_ctx.status, PARSE_ERR);
d3dx9: Add instruction modifiers (sm 2.0+) support to the shader assembler.
2010-04-21 16:15:46 +02:00
$$.shift = $1.shift;
} else {
$$.shift = $1.shift | $2.shift;
}
}
d3dx9: Add shift modifiers parsing to the shader assembler.
2010-07-20 15:01:16 +02:00
omodifier: SHIFT_X2
{
$$.mod = 0;
$$.shift = 1;
}
| SHIFT_X4
{
$$.mod = 0;
$$.shift = 2;
}
| SHIFT_X8
{
$$.mod = 0;
$$.shift = 3;
}
| SHIFT_D2
{
$$.mod = 0;
$$.shift = 15;
}
| SHIFT_D4
{
$$.mod = 0;
$$.shift = 14;
}
| SHIFT_D8
{
$$.mod = 0;
$$.shift = 13;
}
| MOD_SAT
d3dx9: Add instruction modifiers (sm 2.0+) support to the shader assembler.
2010-04-21 16:15:46 +02:00
{
$$.mod = BWRITERSPDM_SATURATE;
$$.shift = 0;
}
| MOD_PP
{
$$.mod = BWRITERSPDM_PARTIALPRECISION;
$$.shift = 0;
}
| MOD_CENTROID
{
$$.mod = BWRITERSPDM_MSAMPCENTROID;
$$.shift = 0;
}
d3dx9: Implement D3DXAssembleShader function, really basic shader assembler. Currently it only accepts a minimal subset of the syntax (e.g. just an instruction and two register types supported) and doesn't produce any real output (i.e. shader bytecode).
2010-03-28 21:16:09 +02:00
sregs: sreg
{
$$.reg[0] = $1;
$$.count = 1;
}
| sregs ',' sreg
{
if($$.count == MAX_SRC_REGS){
asmparser_message(&asm_ctx, "Line %u: Too many source registers in this instruction\n",
asm_ctx.line_no);
d3dcompiler: Make set_parse_status() more general.
2012-05-08 16:17:30 +02:00
set_parse_status(&asm_ctx.status, PARSE_ERR);
d3dx9: Implement D3DXAssembleShader function, really basic shader assembler. Currently it only accepts a minimal subset of the syntax (e.g. just an instruction and two register types supported) and doesn't produce any real output (i.e. shader bytecode).
2010-03-28 21:16:09 +02:00
}
else
$$.reg[$$.count++] = $3;
}
sreg: sreg_name rel_reg swizzle
{
$$.type = $1.type;
$$.regnum = $1.regnum;
d3dcompiler_43: Don't use nameless unions in our private structures to avoid trouble with compilers where they are not supported.
2010-08-29 23:40:33 +02:00
$$.u.swizzle = $3;
d3dx9: Implement D3DXAssembleShader function, really basic shader assembler. Currently it only accepts a minimal subset of the syntax (e.g. just an instruction and two register types supported) and doesn't produce any real output (i.e. shader bytecode).
2010-03-28 21:16:09 +02:00
$$.srcmod = BWRITERSPSM_NONE;
set_rel_reg(&$$, &$2);
}
d3dx9: Add source register modifiers (sm 2+) support to the shader assembler.
2010-04-21 16:15:46 +02:00
| sreg_name rel_reg smod swizzle
{
$$.type = $1.type;
$$.regnum = $1.regnum;
set_rel_reg(&$$, &$2);
$$.srcmod = $3;
d3dcompiler_43: Don't use nameless unions in our private structures to avoid trouble with compilers where they are not supported.
2010-08-29 23:40:33 +02:00
$$.u.swizzle = $4;
d3dx9: Add source register modifiers (sm 2+) support to the shader assembler.
2010-04-21 16:15:46 +02:00
}
| '-' sreg_name rel_reg swizzle
{
$$.type = $2.type;
$$.regnum = $2.regnum;
$$.srcmod = BWRITERSPSM_NEG;
set_rel_reg(&$$, &$3);
d3dcompiler_43: Don't use nameless unions in our private structures to avoid trouble with compilers where they are not supported.
2010-08-29 23:40:33 +02:00
$$.u.swizzle = $4;
d3dx9: Add source register modifiers (sm 2+) support to the shader assembler.
2010-04-21 16:15:46 +02:00
}
| '-' sreg_name rel_reg smod swizzle
{
$$.type = $2.type;
$$.regnum = $2.regnum;
set_rel_reg(&$$, &$3);
switch($4) {
d3dx9: Add ps_1_x source register modifiers to the shader assembler.
2010-07-20 15:01:16 +02:00
case BWRITERSPSM_BIAS: $$.srcmod = BWRITERSPSM_BIASNEG; break;
case BWRITERSPSM_X2: $$.srcmod = BWRITERSPSM_X2NEG; break;
case BWRITERSPSM_SIGN: $$.srcmod = BWRITERSPSM_SIGNNEG; break;
d3dx9: Add source register modifiers (sm 2+) support to the shader assembler.
2010-04-21 16:15:46 +02:00
case BWRITERSPSM_ABS: $$.srcmod = BWRITERSPSM_ABSNEG; break;
d3dx9: Add ps_1_x source register modifiers to the shader assembler.
2010-07-20 15:01:16 +02:00
case BWRITERSPSM_DZ:
asmparser_message(&asm_ctx, "Line %u: Incompatible source modifiers: NEG and DZ\n",
asm_ctx.line_no);
d3dcompiler: Make set_parse_status() more general.
2012-05-08 16:17:30 +02:00
set_parse_status(&asm_ctx.status, PARSE_ERR);
d3dx9: Add ps_1_x source register modifiers to the shader assembler.
2010-07-20 15:01:16 +02:00
break;
case BWRITERSPSM_DW:
asmparser_message(&asm_ctx, "Line %u: Incompatible source modifiers: NEG and DW\n",
asm_ctx.line_no);
d3dcompiler: Make set_parse_status() more general.
2012-05-08 16:17:30 +02:00
set_parse_status(&asm_ctx.status, PARSE_ERR);
d3dx9: Add ps_1_x source register modifiers to the shader assembler.
2010-07-20 15:01:16 +02:00
break;
d3dx9: Add source register modifiers (sm 2+) support to the shader assembler.
2010-04-21 16:15:46 +02:00
default:
FIXME("Unhandled combination of NEGATE and %u\n", $4);
}
d3dcompiler_43: Don't use nameless unions in our private structures to avoid trouble with compilers where they are not supported.
2010-08-29 23:40:33 +02:00
$$.u.swizzle = $5;
d3dx9: Add source register modifiers (sm 2+) support to the shader assembler.
2010-04-21 16:15:46 +02:00
}
d3dx9: Add ps_1_x source register modifiers to the shader assembler.
2010-07-20 15:01:16 +02:00
| IMMVAL '-' sreg_name rel_reg swizzle
{
if($1.val != 1.0 || (!$1.integer)) {
asmparser_message(&asm_ctx, "Line %u: Only \"1 - reg\" is valid for D3DSPSM_COMP, "
"%g - reg found\n", asm_ctx.line_no, $1.val);
d3dcompiler: Make set_parse_status() more general.
2012-05-08 16:17:30 +02:00
set_parse_status(&asm_ctx.status, PARSE_ERR);
d3dx9: Add ps_1_x source register modifiers to the shader assembler.
2010-07-20 15:01:16 +02:00
}
/* Complement - not compatible with other source modifiers */
$$.type = $3.type;
$$.regnum = $3.regnum;
$$.srcmod = BWRITERSPSM_COMP;
set_rel_reg(&$$, &$4);
d3dcompiler_43: Don't use nameless unions in our private structures to avoid trouble with compilers where they are not supported.
2010-08-29 23:40:33 +02:00
$$.u.swizzle = $5;
d3dx9: Add ps_1_x source register modifiers to the shader assembler.
2010-07-20 15:01:16 +02:00
}
| IMMVAL '-' sreg_name rel_reg smod swizzle
{
/* For nicer error reporting */
if($1.val != 1.0 || (!$1.integer)) {
asmparser_message(&asm_ctx, "Line %u: Only \"1 - reg\" is valid for D3DSPSM_COMP\n",
asm_ctx.line_no);
d3dcompiler: Make set_parse_status() more general.
2012-05-08 16:17:30 +02:00
set_parse_status(&asm_ctx.status, PARSE_ERR);
d3dx9: Add ps_1_x source register modifiers to the shader assembler.
2010-07-20 15:01:16 +02:00
} else {
asmparser_message(&asm_ctx, "Line %u: Incompatible source modifiers: D3DSPSM_COMP and %s\n",
asm_ctx.line_no,
debug_print_srcmod($5));
d3dcompiler: Make set_parse_status() more general.
2012-05-08 16:17:30 +02:00
set_parse_status(&asm_ctx.status, PARSE_ERR);
d3dx9: Add ps_1_x source register modifiers to the shader assembler.
2010-07-20 15:01:16 +02:00
}
}
d3dx9: Support some flow control instructions in the shader assembler.
2010-05-11 20:29:07 +02:00
| SMOD_NOT sreg_name swizzle
{
$$.type = $2.type;
$$.regnum = $2.regnum;
$$.rel_reg = NULL;
$$.srcmod = BWRITERSPSM_NOT;
d3dcompiler_43: Don't use nameless unions in our private structures to avoid trouble with compilers where they are not supported.
2010-08-29 23:40:33 +02:00
$$.u.swizzle = $3;
d3dx9: Support some flow control instructions in the shader assembler.
2010-05-11 20:29:07 +02:00
}
d3dx9: Implement D3DXAssembleShader function, really basic shader assembler. Currently it only accepts a minimal subset of the syntax (e.g. just an instruction and two register types supported) and doesn't produce any real output (i.e. shader bytecode).
2010-03-28 21:16:09 +02:00
rel_reg: /* empty */
{
$$.has_rel_reg = FALSE;
$$.additional_offset = 0;
}
d3dx9: Add relative addressing support to the shader assembler.
2010-05-05 19:55:26 +02:00
| '[' immsum ']'
{
$$.has_rel_reg = FALSE;
$$.additional_offset = $2.val;
}
| '[' relreg_name swizzle ']'
{
$$.has_rel_reg = TRUE;
$$.type = $2.type;
$$.additional_offset = 0;
$$.rel_regnum = $2.regnum;
$$.swizzle = $3;
}
| '[' immsum '+' relreg_name swizzle ']'
{
$$.has_rel_reg = TRUE;
$$.type = $4.type;
$$.additional_offset = $2.val;
$$.rel_regnum = $4.regnum;
$$.swizzle = $5;
}
| '[' relreg_name swizzle '+' immsum ']'
{
$$.has_rel_reg = TRUE;
$$.type = $2.type;
$$.additional_offset = $5.val;
$$.rel_regnum = $2.regnum;
$$.swizzle = $3;
}
| '[' immsum '+' relreg_name swizzle '+' immsum ']'
{
$$.has_rel_reg = TRUE;
$$.type = $4.type;
$$.additional_offset = $2.val + $7.val;
$$.rel_regnum = $4.regnum;
$$.swizzle = $5;
}
immsum: IMMVAL
{
if(!$1.integer) {
asmparser_message(&asm_ctx, "Line %u: Unexpected float %f\n",
asm_ctx.line_no, $1.val);
d3dcompiler: Make set_parse_status() more general.
2012-05-08 16:17:30 +02:00
set_parse_status(&asm_ctx.status, PARSE_ERR);
d3dx9: Add relative addressing support to the shader assembler.
2010-05-05 19:55:26 +02:00
}
$$.val = $1.val;
}
| immsum '+' IMMVAL
{
if(!$3.integer) {
asmparser_message(&asm_ctx, "Line %u: Unexpected float %f\n",
asm_ctx.line_no, $3.val);
d3dcompiler: Make set_parse_status() more general.
2012-05-08 16:17:30 +02:00
set_parse_status(&asm_ctx.status, PARSE_ERR);
d3dx9: Add relative addressing support to the shader assembler.
2010-05-05 19:55:26 +02:00
}
$$.val = $1.val + $3.val;
}
d3dx9: Implement D3DXAssembleShader function, really basic shader assembler. Currently it only accepts a minimal subset of the syntax (e.g. just an instruction and two register types supported) and doesn't produce any real output (i.e. shader bytecode).
2010-03-28 21:16:09 +02:00
d3dx9: Add ps_1_x source register modifiers to the shader assembler.
2010-07-20 15:01:16 +02:00
smod: SMOD_BIAS
{
$$ = BWRITERSPSM_BIAS;
}
| SHIFT_X2
{
$$ = BWRITERSPSM_X2;
}
| SMOD_SCALEBIAS
{
$$ = BWRITERSPSM_SIGN;
}
| SMOD_DZ
{
$$ = BWRITERSPSM_DZ;
}
| SMOD_DW
{
$$ = BWRITERSPSM_DW;
}
| SMOD_ABS
d3dx9: Add source register modifiers (sm 2+) support to the shader assembler.
2010-04-21 16:15:46 +02:00
{
$$ = BWRITERSPSM_ABS;
}
d3dx9: Add relative addressing support to the shader assembler.
2010-05-05 19:55:26 +02:00
relreg_name: REG_ADDRESS
{
$$.regnum = 0; $$.type = BWRITERSPR_ADDR;
}
| REG_LOOP
{
$$.regnum = 0; $$.type = BWRITERSPR_LOOP;
}
d3dx9: Implement D3DXAssembleShader function, really basic shader assembler. Currently it only accepts a minimal subset of the syntax (e.g. just an instruction and two register types supported) and doesn't produce any real output (i.e. shader bytecode).
2010-03-28 21:16:09 +02:00
sreg_name: REG_TEMP
{
$$.regnum = $1; $$.type = BWRITERSPR_TEMP;
}
d3dx9: Support all the remaining register types in the shader assembler.
2010-05-05 16:56:09 +02:00
| REG_OUTPUT
{
asmparser_message(&asm_ctx, "Line %u: Register o%u is not a valid source register\n",
asm_ctx.line_no, $1);
d3dcompiler: Make set_parse_status() more general.
2012-05-08 16:17:30 +02:00
set_parse_status(&asm_ctx.status, PARSE_WARN);
d3dx9: Support all the remaining register types in the shader assembler.
2010-05-05 16:56:09 +02:00
}
| REG_INPUT
{
$$.regnum = $1; $$.type = BWRITERSPR_INPUT;
}
d3dx9: Implement D3DXAssembleShader function, really basic shader assembler. Currently it only accepts a minimal subset of the syntax (e.g. just an instruction and two register types supported) and doesn't produce any real output (i.e. shader bytecode).
2010-03-28 21:16:09 +02:00
| REG_CONSTFLOAT
{
$$.regnum = $1; $$.type = BWRITERSPR_CONST;
}
d3dx9: Support all the remaining register types in the shader assembler.
2010-05-05 16:56:09 +02:00
| REG_CONSTINT
{
$$.regnum = $1; $$.type = BWRITERSPR_CONSTINT;
}
| REG_CONSTBOOL
{
$$.regnum = $1; $$.type = BWRITERSPR_CONSTBOOL;
}
| REG_TEXTURE
{
$$.regnum = $1; $$.type = BWRITERSPR_TEXTURE;
}
| REG_TEXCRDOUT
{
asmparser_message(&asm_ctx, "Line %u: Register oT%u is not a valid source register\n",
asm_ctx.line_no, $1);
d3dcompiler: Make set_parse_status() more general.
2012-05-08 16:17:30 +02:00
set_parse_status(&asm_ctx.status, PARSE_WARN);
d3dx9: Support all the remaining register types in the shader assembler.
2010-05-05 16:56:09 +02:00
}
| REG_SAMPLER
{
$$.regnum = $1; $$.type = BWRITERSPR_SAMPLER;
}
| REG_OPOS
{
asmparser_message(&asm_ctx, "Line %u: Register oPos is not a valid source register\n",
asm_ctx.line_no);
d3dcompiler: Make set_parse_status() more general.
2012-05-08 16:17:30 +02:00
set_parse_status(&asm_ctx.status, PARSE_WARN);
d3dx9: Support all the remaining register types in the shader assembler.
2010-05-05 16:56:09 +02:00
}
| REG_OFOG
{
asmparser_message(&asm_ctx, "Line %u: Register oFog is not a valid source register\n",
asm_ctx.line_no);
d3dcompiler: Make set_parse_status() more general.
2012-05-08 16:17:30 +02:00
set_parse_status(&asm_ctx.status, PARSE_WARN);
d3dx9: Support all the remaining register types in the shader assembler.
2010-05-05 16:56:09 +02:00
}
| REG_VERTEXCOLOR
{
asmparser_message(&asm_ctx, "Line %u: Register oD%u is not a valid source register\n",
asm_ctx.line_no, $1);
d3dcompiler: Make set_parse_status() more general.
2012-05-08 16:17:30 +02:00
set_parse_status(&asm_ctx.status, PARSE_WARN);
d3dx9: Support all the remaining register types in the shader assembler.
2010-05-05 16:56:09 +02:00
}
| REG_FRAGCOLOR
{
asmparser_message(&asm_ctx, "Line %u: Register oC%u is not a valid source register\n",
asm_ctx.line_no, $1);
d3dcompiler: Make set_parse_status() more general.
2012-05-08 16:17:30 +02:00
set_parse_status(&asm_ctx.status, PARSE_WARN);
d3dx9: Support all the remaining register types in the shader assembler.
2010-05-05 16:56:09 +02:00
}
| REG_FRAGDEPTH
{
asmparser_message(&asm_ctx, "Line %u: Register oDepth is not a valid source register\n",
asm_ctx.line_no);
d3dcompiler: Make set_parse_status() more general.
2012-05-08 16:17:30 +02:00
set_parse_status(&asm_ctx.status, PARSE_WARN);
d3dx9: Support all the remaining register types in the shader assembler.
2010-05-05 16:56:09 +02:00
}
| REG_PREDICATE
{
$$.regnum = 0; $$.type = BWRITERSPR_PREDICATE;
}
| REG_VPOS
{
$$.regnum = 0; $$.type = BWRITERSPR_MISCTYPE;
}
| REG_VFACE
{
$$.regnum = 1; $$.type = BWRITERSPR_MISCTYPE;
}
| REG_ADDRESS
{
$$.regnum = 0; $$.type = BWRITERSPR_ADDR;
}
| REG_LOOP
{
$$.regnum = 0; $$.type = BWRITERSPR_LOOP;
}
| REG_LABEL
{
$$.regnum = $1; $$.type = BWRITERSPR_LABEL;
}
d3dx9: Implement D3DXAssembleShader function, really basic shader assembler. Currently it only accepts a minimal subset of the syntax (e.g. just an instruction and two register types supported) and doesn't produce any real output (i.e. shader bytecode).
2010-03-28 21:16:09 +02:00
d3dx9: Add other flow control instructions in the shader assembler.
2009-11-24 02:08:32 +01:00
comp: COMP_GT { $$ = BWRITER_COMPARISON_GT; }
| COMP_LT { $$ = BWRITER_COMPARISON_LT; }
| COMP_GE { $$ = BWRITER_COMPARISON_GE; }
| COMP_LE { $$ = BWRITER_COMPARISON_LE; }
| COMP_EQ { $$ = BWRITER_COMPARISON_EQ; }
| COMP_NE { $$ = BWRITER_COMPARISON_NE; }
d3dx9: Add output dcl instruction partial support to the shader assembler.
2010-05-13 17:21:58 +02:00
dclusage: USAGE_POSITION
{
TRACE("dcl_position%u\n", $1);
$$.regnum = $1;
$$.dclusage = BWRITERDECLUSAGE_POSITION;
}
d3dx9: Complete output dcl instruction support.
2010-05-13 17:21:58 +02:00
| USAGE_BLENDWEIGHT
{
TRACE("dcl_blendweight%u\n", $1);
$$.regnum = $1;
$$.dclusage = BWRITERDECLUSAGE_BLENDWEIGHT;
}
| USAGE_BLENDINDICES
{
TRACE("dcl_blendindices%u\n", $1);
$$.regnum = $1;
$$.dclusage = BWRITERDECLUSAGE_BLENDINDICES;
}
| USAGE_NORMAL
{
TRACE("dcl_normal%u\n", $1);
$$.regnum = $1;
$$.dclusage = BWRITERDECLUSAGE_NORMAL;
}
| USAGE_PSIZE
{
TRACE("dcl_psize%u\n", $1);
$$.regnum = $1;
$$.dclusage = BWRITERDECLUSAGE_PSIZE;
}
| USAGE_TEXCOORD
{
TRACE("dcl_texcoord%u\n", $1);
$$.regnum = $1;
$$.dclusage = BWRITERDECLUSAGE_TEXCOORD;
}
| USAGE_TANGENT
{
TRACE("dcl_tangent%u\n", $1);
$$.regnum = $1;
$$.dclusage = BWRITERDECLUSAGE_TANGENT;
}
| USAGE_BINORMAL
{
TRACE("dcl_binormal%u\n", $1);
$$.regnum = $1;
$$.dclusage = BWRITERDECLUSAGE_BINORMAL;
}
| USAGE_TESSFACTOR
{
TRACE("dcl_tessfactor%u\n", $1);
$$.regnum = $1;
$$.dclusage = BWRITERDECLUSAGE_TESSFACTOR;
}
| USAGE_POSITIONT
{
TRACE("dcl_positiont%u\n", $1);
$$.regnum = $1;
$$.dclusage = BWRITERDECLUSAGE_POSITIONT;
}
| USAGE_COLOR
{
TRACE("dcl_color%u\n", $1);
$$.regnum = $1;
$$.dclusage = BWRITERDECLUSAGE_COLOR;
}
| USAGE_FOG
{
TRACE("dcl_fog%u\n", $1);
$$.regnum = $1;
$$.dclusage = BWRITERDECLUSAGE_FOG;
}
| USAGE_DEPTH
{
TRACE("dcl_depth%u\n", $1);
$$.regnum = $1;
$$.dclusage = BWRITERDECLUSAGE_DEPTH;
}
| USAGE_SAMPLE
{
TRACE("dcl_sample%u\n", $1);
$$.regnum = $1;
$$.dclusage = BWRITERDECLUSAGE_SAMPLE;
}
d3dx9: Add output dcl instruction partial support to the shader assembler.
2010-05-13 17:21:58 +02:00
d3dx9: Accept texture coordinate registers in dcl instruction.
2010-06-08 00:53:23 +02:00
dcl_inputreg: REG_INPUT
{
$$.regnum = $1; $$.type = BWRITERSPR_INPUT;
}
| REG_TEXTURE
{
$$.regnum = $1; $$.type = BWRITERSPR_TEXTURE;
}
d3dx9: Add sampler dcl instruction support to the shader assembler.
2010-05-13 17:21:59 +02:00
sampdcl: SAMPTYPE_1D
{
$$ = BWRITERSTT_1D;
}
| SAMPTYPE_2D
{
$$ = BWRITERSTT_2D;
}
| SAMPTYPE_CUBE
{
$$ = BWRITERSTT_CUBE;
}
| SAMPTYPE_VOLUME
{
$$ = BWRITERSTT_VOLUME;
}
d3dx9: Add predicate support to the shader assembler.
2010-05-11 20:29:07 +02:00
predicate: '(' REG_PREDICATE swizzle ')'
{
$$.type = BWRITERSPR_PREDICATE;
$$.regnum = 0;
$$.rel_reg = NULL;
$$.srcmod = BWRITERSPSM_NONE;
d3dcompiler_43: Don't use nameless unions in our private structures to avoid trouble with compilers where they are not supported.
2010-08-29 23:40:33 +02:00
$$.u.swizzle = $3;
d3dx9: Add predicate support to the shader assembler.
2010-05-11 20:29:07 +02:00
}
| '(' SMOD_NOT REG_PREDICATE swizzle ')'
{
$$.type = BWRITERSPR_PREDICATE;
$$.regnum = 0;
$$.rel_reg = NULL;
$$.srcmod = BWRITERSPSM_NOT;
d3dcompiler_43: Don't use nameless unions in our private structures to avoid trouble with compilers where they are not supported.
2010-08-29 23:40:33 +02:00
$$.u.swizzle = $4;
d3dx9: Add predicate support to the shader assembler.
2010-05-11 20:29:07 +02:00
}
d3dx9: Implement D3DXAssembleShader function, really basic shader assembler. Currently it only accepts a minimal subset of the syntax (e.g. just an instruction and two register types supported) and doesn't produce any real output (i.e. shader bytecode).
2010-03-28 21:16:09 +02:00
%%
d3dcompiler: Generalize message reporting function.
2012-05-08 16:17:31 +02:00
struct bwriter_shader *parse_asm_shader(char **messages)
{
d3dx9: Implement D3DXAssembleShader function, really basic shader assembler. Currently it only accepts a minimal subset of the syntax (e.g. just an instruction and two register types supported) and doesn't produce any real output (i.e. shader bytecode).
2010-03-28 21:16:09 +02:00
struct bwriter_shader *ret = NULL;
asm_ctx.shader = NULL;
asm_ctx.status = PARSE_SUCCESS;
d3dcompiler: Generalize message reporting function.
2012-05-08 16:17:31 +02:00
asm_ctx.messages.size = asm_ctx.messages.capacity = 0;
d3dx9: Implement D3DXAssembleShader function, really basic shader assembler. Currently it only accepts a minimal subset of the syntax (e.g. just an instruction and two register types supported) and doesn't produce any real output (i.e. shader bytecode).
2010-03-28 21:16:09 +02:00
asm_ctx.line_no = 1;
asmshader_parse();
d3dcompiler: Generalize message reporting function.
2012-05-08 16:17:31 +02:00
if (asm_ctx.status != PARSE_ERR)
ret = asm_ctx.shader;
else if (asm_ctx.shader)
SlDeleteShader(asm_ctx.shader);
d3dx9: Implement D3DXAssembleShader function, really basic shader assembler. Currently it only accepts a minimal subset of the syntax (e.g. just an instruction and two register types supported) and doesn't produce any real output (i.e. shader bytecode).
2010-03-28 21:16:09 +02:00
d3dcompiler: Generalize message reporting function.
2012-05-08 16:17:31 +02:00
if (messages)
{
if (asm_ctx.messages.size)
{
d3dx9: Implement D3DXAssembleShader function, really basic shader assembler. Currently it only accepts a minimal subset of the syntax (e.g. just an instruction and two register types supported) and doesn't produce any real output (i.e. shader bytecode).
2010-03-28 21:16:09 +02:00
/* Shrink the buffer to the used size */
d3dcompiler: Rename asm_alloc/realloc/free functions to more generic names.
2012-05-08 16:17:32 +02:00
*messages = d3dcompiler_realloc(asm_ctx.messages.string, asm_ctx.messages.size + 1);
if (!*messages)
{
d3dx9: Implement D3DXAssembleShader function, really basic shader assembler. Currently it only accepts a minimal subset of the syntax (e.g. just an instruction and two register types supported) and doesn't produce any real output (i.e. shader bytecode).
2010-03-28 21:16:09 +02:00
ERR("Out of memory, no messages reported\n");
d3dcompiler: Rename asm_alloc/realloc/free functions to more generic names.
2012-05-08 16:17:32 +02:00
d3dcompiler_free(asm_ctx.messages.string);
d3dx9: Implement D3DXAssembleShader function, really basic shader assembler. Currently it only accepts a minimal subset of the syntax (e.g. just an instruction and two register types supported) and doesn't produce any real output (i.e. shader bytecode).
2010-03-28 21:16:09 +02:00
}
d3dcompiler: Rename asm_alloc/realloc/free functions to more generic names.
2012-05-08 16:17:32 +02:00
}
else
{
d3dx9: Implement D3DXAssembleShader function, really basic shader assembler. Currently it only accepts a minimal subset of the syntax (e.g. just an instruction and two register types supported) and doesn't produce any real output (i.e. shader bytecode).
2010-03-28 21:16:09 +02:00
*messages = NULL;
}
d3dcompiler: Rename asm_alloc/realloc/free functions to more generic names.
2012-05-08 16:17:32 +02:00
}
else
{
if (asm_ctx.messages.capacity)
d3dcompiler_free(asm_ctx.messages.string);
d3dx9: Implement D3DXAssembleShader function, really basic shader assembler. Currently it only accepts a minimal subset of the syntax (e.g. just an instruction and two register types supported) and doesn't produce any real output (i.e. shader bytecode).
2010-03-28 21:16:09 +02:00
}
return ret;
}