d3dx9: Add other flow control instructions in the shader assembler.
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25c929ab61
commit
93b2648c49
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@ -50,8 +50,9 @@ static void asmparser_instr(struct asm_parser *This, DWORD opcode,
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if(!This->shader) return;
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TRACE_(parsed_shader)("%s%s ", debug_print_opcode(opcode),
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debug_print_dstmod(mod));
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TRACE_(parsed_shader)("%s%s%s ", debug_print_opcode(opcode),
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debug_print_dstmod(mod),
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debug_print_comp(comp));
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if(dst) {
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TRACE_(parsed_shader)("%s", debug_print_dstreg(dst, This->shader->type));
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firstreg = FALSE;
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@ -243,6 +243,14 @@ ps_3_0 {return VER_PS30; }
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\_pp {return MOD_PP; }
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\_centroid {return MOD_CENTROID; }
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/* compare params */
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\_gt {return COMP_GT; }
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\_lt {return COMP_LT; }
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\_ge {return COMP_GE; }
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\_le {return COMP_LE; }
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\_eq {return COMP_EQ; }
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\_ne {return COMP_NE; }
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{IMMVAL} {
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asmshader_lval.immval.val = atof(yytext);
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asmshader_lval.immval.integer = ((strstr(yytext, ".") == NULL) && (strstr(yytext, "f") == NULL));
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@ -79,6 +79,7 @@ void set_rel_reg(struct shader_reg *reg, struct rel_reg *rel) {
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DWORD mod;
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DWORD shift;
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} modshift;
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BWRITER_COMPARISON_TYPE comptype;
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struct rel_reg rel_reg;
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struct src_regs sregs;
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}
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@ -178,6 +179,14 @@ void set_rel_reg(struct shader_reg *reg, struct rel_reg *rel) {
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%token MOD_PP
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%token MOD_CENTROID
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/* Compare tokens */
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%token COMP_GT
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%token COMP_LT
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%token COMP_GE
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%token COMP_LE
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%token COMP_EQ
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%token COMP_NE
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/* Source register modifiers */
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%token SMOD_ABS
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%token SMOD_NOT
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@ -198,6 +207,7 @@ void set_rel_reg(struct shader_reg *reg, struct rel_reg *rel) {
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%type <sw_components> sw_components
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%type <modshift> omods
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%type <modshift> omodifier
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%type <comptype> comp
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%type <rel_reg> rel_reg
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%type <immval> immsum
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%type <sregs> sregs
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@ -473,6 +483,11 @@ instruction: INSTR_ADD omods dreg ',' sregs
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TRACE("IF\n");
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asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_IF, 0, 0, 0, 0, &$2, 1);
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}
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| INSTR_IF comp sregs
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{
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TRACE("IFC\n");
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asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_IFC, 0, 0, $2, 0, &$3, 2);
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}
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| INSTR_ELSE
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{
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TRACE("ELSE\n");
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@ -488,6 +503,11 @@ instruction: INSTR_ADD omods dreg ',' sregs
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TRACE("BREAK\n");
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asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_BREAK, 0, 0, 0, 0, 0, 0);
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}
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| INSTR_BREAK comp sregs
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{
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TRACE("BREAKC\n");
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asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_BREAKC, 0, 0, $2, 0, &$3, 2);
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}
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| INSTR_CALL sregs
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{
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TRACE("CALL\n");
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@ -996,6 +1016,13 @@ sreg_name: REG_TEMP
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$$.regnum = $1; $$.type = BWRITERSPR_LABEL;
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}
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comp: COMP_GT { $$ = BWRITER_COMPARISON_GT; }
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| COMP_LT { $$ = BWRITER_COMPARISON_LT; }
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| COMP_GE { $$ = BWRITER_COMPARISON_GE; }
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| COMP_LE { $$ = BWRITER_COMPARISON_LE; }
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| COMP_EQ { $$ = BWRITER_COMPARISON_EQ; }
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| COMP_NE { $$ = BWRITER_COMPARISON_NE; }
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%%
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void asmshader_error (char const *s) {
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@ -91,6 +91,20 @@ DWORD d3d9_dstmod(DWORD bwriter_mod) {
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return ret;
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}
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DWORD d3d9_comparetype(DWORD asmshader_comparetype) {
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switch(asmshader_comparetype) {
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case BWRITER_COMPARISON_GT: return D3DSPC_GT;
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case BWRITER_COMPARISON_EQ: return D3DSPC_EQ;
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case BWRITER_COMPARISON_GE: return D3DSPC_GE;
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case BWRITER_COMPARISON_LT: return D3DSPC_LT;
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case BWRITER_COMPARISON_NE: return D3DSPC_NE;
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case BWRITER_COMPARISON_LE: return D3DSPC_LE;
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default:
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FIXME("Unexpected BWRITER_COMPARISON type %u\n", asmshader_comparetype);
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return 0;
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}
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}
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DWORD d3d9_register(DWORD bwriter_register) {
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if(bwriter_register == BWRITERSPR_TEMP) return D3DSPR_TEMP;
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if(bwriter_register == BWRITERSPR_INPUT) return D3DSPR_INPUT;
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@ -157,9 +171,11 @@ DWORD d3d9_opcode(DWORD bwriter_opcode) {
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case BWRITERSIO_REP: return D3DSIO_REP;
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case BWRITERSIO_ENDREP: return D3DSIO_ENDREP;
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case BWRITERSIO_IF: return D3DSIO_IF;
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case BWRITERSIO_IFC: return D3DSIO_IFC;
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case BWRITERSIO_ELSE: return D3DSIO_ELSE;
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case BWRITERSIO_ENDIF: return D3DSIO_ENDIF;
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case BWRITERSIO_BREAK: return D3DSIO_BREAK;
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case BWRITERSIO_BREAKC: return D3DSIO_BREAKC;
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case BWRITERSIO_MOVA: return D3DSIO_MOVA;
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case BWRITERSIO_EXPP: return D3DSIO_EXPP;
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case BWRITERSIO_LOGP: return D3DSIO_LOGP;
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@ -362,6 +378,19 @@ const char *debug_print_srcreg(const struct shader_reg *reg, shader_type st) {
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return "Unknown modifier";
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}
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const char *debug_print_comp(DWORD comp) {
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switch(comp) {
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case BWRITER_COMPARISON_NONE: return "";
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case BWRITER_COMPARISON_GT: return "_gt";
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case BWRITER_COMPARISON_EQ: return "_eq";
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case BWRITER_COMPARISON_GE: return "_ge";
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case BWRITER_COMPARISON_LT: return "_lt";
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case BWRITER_COMPARISON_NE: return "_ne";
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case BWRITER_COMPARISON_LE: return "_le";
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default: return "_unknown";
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}
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}
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const char *debug_print_opcode(DWORD opcode) {
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switch(opcode){
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case BWRITERSIO_NOP: return "nop";
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@ -404,9 +433,11 @@ const char *debug_print_opcode(DWORD opcode) {
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case BWRITERSIO_REP: return "rep";
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case BWRITERSIO_ENDREP: return "endrep";
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case BWRITERSIO_IF: return "if";
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case BWRITERSIO_IFC: return "ifc";
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case BWRITERSIO_ELSE: return "else";
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case BWRITERSIO_ENDIF: return "endif";
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case BWRITERSIO_BREAK: return "break";
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case BWRITERSIO_BREAKC: return "breakc";
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case BWRITERSIO_MOVA: return "mova";
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case BWRITERSIO_EXPP: return "expp";
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case BWRITERSIO_LOGP: return "logp";
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@ -196,6 +196,8 @@ static void sm_2_opcode(struct bc_writer *This,
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/* From sm 2 onwards instruction length is encoded in the opcode field */
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int dsts = instr->has_dst ? 1 : 0;
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token |= instrlen(instr, instr->num_srcs, dsts) << D3DSI_INSTLENGTH_SHIFT;
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if(instr->comptype)
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token |= (d3d9_comparetype(instr->comptype) << 16) & (0xf << 16);
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put_dword(buffer,token);
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}
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@ -324,9 +326,11 @@ static const struct instr_handler_table vs_3_handlers[] = {
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{BWRITERSIO_ENDREP, instr_handler},
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{BWRITERSIO_IF, instr_handler},
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{BWRITERSIO_LABEL, instr_handler},
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{BWRITERSIO_IFC, instr_handler},
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{BWRITERSIO_ELSE, instr_handler},
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{BWRITERSIO_ENDIF, instr_handler},
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{BWRITERSIO_BREAK, instr_handler},
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{BWRITERSIO_BREAKC, instr_handler},
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{BWRITERSIO_LOOP, instr_handler},
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{BWRITERSIO_RET, instr_handler},
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{BWRITERSIO_ENDLOOP, instr_handler},
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@ -137,7 +137,13 @@ typedef enum _shader_type {
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} shader_type;
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typedef enum BWRITER_COMPARISON_TYPE {
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BWRITER_COMPARISON_NONE = 0,
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BWRITER_COMPARISON_NONE,
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BWRITER_COMPARISON_GT,
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BWRITER_COMPARISON_EQ,
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BWRITER_COMPARISON_GE,
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BWRITER_COMPARISON_LT,
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BWRITER_COMPARISON_NE,
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BWRITER_COMPARISON_LE
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} BWRITER_COMPARISON_TYPE;
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struct shader_reg {
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@ -345,6 +351,7 @@ const char *debug_print_dstreg(const struct shader_reg *reg, shader_type st);
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const char *debug_print_srcreg(const struct shader_reg *reg, shader_type st);
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const char *debug_print_swizzle(DWORD swizzle);
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const char *debug_print_writemask(DWORD mask);
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const char *debug_print_comp(DWORD comp);
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const char *debug_print_opcode(DWORD opcode);
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/* Utilities for internal->d3d constant mapping */
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@ -352,6 +359,7 @@ DWORD d3d9_swizzle(DWORD bwriter_swizzle);
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DWORD d3d9_writemask(DWORD bwriter_writemask);
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DWORD d3d9_srcmod(DWORD bwriter_srcmod);
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DWORD d3d9_dstmod(DWORD bwriter_mod);
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DWORD d3d9_comparetype(DWORD bwriter_comparetype);
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DWORD d3d9_register(DWORD bwriter_register);
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DWORD d3d9_opcode(DWORD bwriter_opcode);
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@ -403,9 +411,11 @@ typedef enum _BWRITERSHADER_INSTRUCTION_OPCODE_TYPE {
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BWRITERSIO_REP,
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BWRITERSIO_ENDREP,
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BWRITERSIO_IF,
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BWRITERSIO_IFC,
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BWRITERSIO_ELSE,
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BWRITERSIO_ENDIF,
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BWRITERSIO_BREAK,
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BWRITERSIO_BREAKC,
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BWRITERSIO_MOVA,
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BWRITERSIO_EXPP,
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