d3dcompiler_43: Don't use nameless unions in our private structures to avoid trouble with compilers where they are not supported.
This commit is contained in:
parent
e7fbc9dece
commit
aaf78f1a0b
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@ -110,7 +110,7 @@ static void asmparser_dcl_output(struct asm_parser *This, DWORD usage, DWORD num
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asmparser_message(This, "Line %u: Output register declared in a pixel shader\n", This->line_no);
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set_parse_status(This, PARSE_ERR);
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}
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if(!record_declaration(This->shader, usage, num, 0, TRUE, reg->regnum, reg->writemask, FALSE)) {
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if(!record_declaration(This->shader, usage, num, 0, TRUE, reg->regnum, reg->u.writemask, FALSE)) {
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ERR("Out of memory\n");
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set_parse_status(This, PARSE_ERR);
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}
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@ -141,7 +141,7 @@ static void asmparser_dcl_input(struct asm_parser *This, DWORD usage, DWORD num,
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instr.shift = 0;
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This->funcs->dstreg(This, &instr, reg);
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if(!record_declaration(This->shader, usage, num, mod, FALSE, reg->regnum, reg->writemask, FALSE)) {
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if(!record_declaration(This->shader, usage, num, mod, FALSE, reg->regnum, reg->u.writemask, FALSE)) {
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ERR("Out of memory\n");
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set_parse_status(This, PARSE_ERR);
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}
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@ -155,7 +155,7 @@ static void asmparser_dcl_input_ps_2(struct asm_parser *This, DWORD usage, DWORD
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instr.dstmod = mod;
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instr.shift = 0;
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This->funcs->dstreg(This, &instr, reg);
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if(!record_declaration(This->shader, usage, num, mod, FALSE, instr.dst.regnum, instr.dst.writemask, FALSE)) {
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if(!record_declaration(This->shader, usage, num, mod, FALSE, instr.dst.regnum, instr.dst.u.writemask, FALSE)) {
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ERR("Out of memory\n");
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set_parse_status(This, PARSE_ERR);
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}
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@ -396,7 +396,7 @@ static void asmparser_texhelper(struct asm_parser *This, DWORD mod, DWORD shift,
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ZeroMemory(&instr->src[1], sizeof(instr->src[1]));
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instr->src[1].type = BWRITERSPR_SAMPLER;
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instr->src[1].regnum = dst->regnum;
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instr->src[1].swizzle = BWRITERVS_NOSWIZZLE;
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instr->src[1].u.swizzle = BWRITERVS_NOSWIZZLE;
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instr->src[1].srcmod = BWRITERSPSM_NONE;
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instr->src[1].rel_reg = NULL;
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@ -450,7 +450,7 @@ static void asmparser_texld14(struct asm_parser *This, DWORD mod, DWORD shift,
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ZeroMemory(&instr->src[1], sizeof(instr->src[1]));
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instr->src[1].type = BWRITERSPR_SAMPLER;
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instr->src[1].regnum = dst->regnum;
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instr->src[1].swizzle = BWRITERVS_NOSWIZZLE;
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instr->src[1].u.swizzle = BWRITERVS_NOSWIZZLE;
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instr->src[1].srcmod = BWRITERSPSM_NONE;
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instr->src[1].rel_reg = NULL;
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@ -467,7 +467,7 @@ static void asmparser_texreg2ar(struct asm_parser *This, DWORD mod, DWORD shift,
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src = map_oldps_register(src0, FALSE);
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/* Supply the correct swizzle */
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src.swizzle = BWRITERVS_X_W | BWRITERVS_Y_X | BWRITERVS_Z_X | BWRITERVS_W_X;
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src.u.swizzle = BWRITERVS_X_W | BWRITERVS_Y_X | BWRITERVS_Z_X | BWRITERVS_W_X;
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asmparser_texhelper(This, mod, shift, dst, &src);
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}
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@ -478,7 +478,7 @@ static void asmparser_texreg2gb(struct asm_parser *This, DWORD mod, DWORD shift,
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src = map_oldps_register(src0, FALSE);
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/* Supply the correct swizzle */
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src.swizzle = BWRITERVS_X_Y | BWRITERVS_Y_Z | BWRITERVS_Z_Z | BWRITERVS_W_Z;
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src.u.swizzle = BWRITERVS_X_Y | BWRITERVS_Y_Z | BWRITERVS_Z_Z | BWRITERVS_W_Z;
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asmparser_texhelper(This, mod, shift, dst, &src);
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}
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@ -489,7 +489,7 @@ static void asmparser_texreg2rgb(struct asm_parser *This, DWORD mod, DWORD shift
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src = map_oldps_register(src0, FALSE);
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/* Supply the correct swizzle */
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src.swizzle = BWRITERVS_X_X | BWRITERVS_Y_Y | BWRITERVS_Z_Z | BWRITERVS_W_Z;
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src.u.swizzle = BWRITERVS_X_X | BWRITERVS_Y_Y | BWRITERVS_Z_Z | BWRITERVS_W_Z;
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asmparser_texhelper(This, mod, shift, dst, &src);
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}
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@ -618,11 +618,11 @@ static struct shader_reg map_oldvs_register(const struct shader_reg *reg) {
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break;
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case BWRITERSRO_FOG:
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ret.regnum = OFOG_REG;
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ret.writemask = OFOG_WRITEMASK;
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ret.u.writemask = OFOG_WRITEMASK;
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break;
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case BWRITERSRO_POINT_SIZE:
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ret.regnum = OPTS_REG;
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ret.writemask = OPTS_WRITEMASK;
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ret.u.writemask = OPTS_WRITEMASK;
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break;
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default:
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FIXME("Unhandled RASTOUT register %u\n", reg->regnum);
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@ -690,9 +690,9 @@ static void check_abs_srcmod(struct asm_parser *This, DWORD srcmod) {
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static void check_loop_swizzle(struct asm_parser *This,
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const struct shader_reg *src) {
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if((src->type == BWRITERSPR_LOOP && src->swizzle != BWRITERVS_NOSWIZZLE) ||
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if((src->type == BWRITERSPR_LOOP && src->u.swizzle != BWRITERVS_NOSWIZZLE) ||
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(src->rel_reg && src->rel_reg->type == BWRITERSPR_LOOP &&
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src->rel_reg->swizzle != BWRITERVS_NOSWIZZLE)) {
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src->rel_reg->u.swizzle != BWRITERVS_NOSWIZZLE)) {
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asmparser_message(This, "Line %u: Swizzle not allowed on aL register\n", This->line_no);
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set_parse_status(This, PARSE_ERR);
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}
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@ -48,7 +48,7 @@ void set_rel_reg(struct shader_reg *reg, struct rel_reg *rel) {
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return;
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}
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reg->rel_reg->type = rel->type;
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reg->rel_reg->swizzle = rel->swizzle;
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reg->rel_reg->u.swizzle = rel->swizzle;
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reg->rel_reg->regnum = rel->rel_regnum;
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}
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}
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@ -557,7 +557,7 @@ instruction: INSTR_ADD omods dreg ',' sregs
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reg.regnum = $3;
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reg.rel_reg = NULL;
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reg.srcmod = 0;
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reg.writemask = BWRITERSP_WRITEMASK_ALL;
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reg.u.writemask = BWRITERSP_WRITEMASK_ALL;
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asm_ctx.funcs->dcl_output(&asm_ctx, $2.dclusage, $2.regnum, ®);
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}
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| INSTR_DCL dclusage REG_OUTPUT writemask
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@ -569,7 +569,7 @@ instruction: INSTR_ADD omods dreg ',' sregs
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reg.regnum = $3;
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reg.rel_reg = NULL;
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reg.srcmod = 0;
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reg.writemask = $4;
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reg.u.writemask = $4;
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asm_ctx.funcs->dcl_output(&asm_ctx, $2.dclusage, $2.regnum, ®);
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}
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| INSTR_DCL dclusage omods dcl_inputreg
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@ -592,7 +592,7 @@ instruction: INSTR_ADD omods dreg ',' sregs
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reg.regnum = $4.regnum;
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reg.rel_reg = NULL;
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reg.srcmod = 0;
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reg.writemask = BWRITERSP_WRITEMASK_ALL;
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reg.u.writemask = BWRITERSP_WRITEMASK_ALL;
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asm_ctx.funcs->dcl_input(&asm_ctx, $2.dclusage, $2.regnum, $3.mod, ®);
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}
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| INSTR_DCL dclusage omods dcl_inputreg writemask
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@ -615,7 +615,7 @@ instruction: INSTR_ADD omods dreg ',' sregs
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reg.regnum = $4.regnum;
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reg.rel_reg = NULL;
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reg.srcmod = 0;
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reg.writemask = $5;
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reg.u.writemask = $5;
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asm_ctx.funcs->dcl_input(&asm_ctx, $2.dclusage, $2.regnum, $3.mod, ®);
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}
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| INSTR_DCL omods dcl_inputreg
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@ -637,7 +637,7 @@ instruction: INSTR_ADD omods dreg ',' sregs
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reg.regnum = $3.regnum;
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reg.rel_reg = NULL;
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reg.srcmod = 0;
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reg.writemask = BWRITERSP_WRITEMASK_ALL;
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reg.u.writemask = BWRITERSP_WRITEMASK_ALL;
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asm_ctx.funcs->dcl_input(&asm_ctx, 0, 0, $2.mod, ®);
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}
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| INSTR_DCL omods dcl_inputreg writemask
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@ -659,7 +659,7 @@ instruction: INSTR_ADD omods dreg ',' sregs
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reg.regnum = $3.regnum;
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reg.rel_reg = NULL;
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reg.srcmod = 0;
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reg.writemask = $4;
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reg.u.writemask = $4;
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asm_ctx.funcs->dcl_input(&asm_ctx, 0, 0, $2.mod, ®);
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}
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| INSTR_DCL sampdcl omods REG_SAMPLER
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@ -976,7 +976,7 @@ dreg: dreg_name rel_reg
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{
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$$.regnum = $1.regnum;
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$$.type = $1.type;
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$$.writemask = BWRITERSP_WRITEMASK_ALL;
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$$.u.writemask = BWRITERSP_WRITEMASK_ALL;
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$$.srcmod = BWRITERSPSM_NONE;
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set_rel_reg(&$$, &$2);
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}
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@ -984,7 +984,7 @@ dreg: dreg_name rel_reg
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{
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$$.regnum = $1.regnum;
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$$.type = $1.type;
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$$.writemask = $2;
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$$.u.writemask = $2;
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$$.srcmod = BWRITERSPSM_NONE;
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$$.rel_reg = NULL;
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}
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@ -1250,7 +1250,7 @@ sreg: sreg_name rel_reg swizzle
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{
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$$.type = $1.type;
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$$.regnum = $1.regnum;
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$$.swizzle = $3;
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$$.u.swizzle = $3;
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$$.srcmod = BWRITERSPSM_NONE;
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set_rel_reg(&$$, &$2);
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}
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@ -1260,7 +1260,7 @@ sreg: sreg_name rel_reg swizzle
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$$.regnum = $1.regnum;
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set_rel_reg(&$$, &$2);
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$$.srcmod = $3;
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$$.swizzle = $4;
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$$.u.swizzle = $4;
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}
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| '-' sreg_name rel_reg swizzle
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{
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@ -1268,7 +1268,7 @@ sreg: sreg_name rel_reg swizzle
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$$.regnum = $2.regnum;
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$$.srcmod = BWRITERSPSM_NEG;
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set_rel_reg(&$$, &$3);
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$$.swizzle = $4;
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$$.u.swizzle = $4;
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}
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| '-' sreg_name rel_reg smod swizzle
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{
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@ -1293,7 +1293,7 @@ sreg: sreg_name rel_reg swizzle
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default:
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FIXME("Unhandled combination of NEGATE and %u\n", $4);
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}
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$$.swizzle = $5;
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$$.u.swizzle = $5;
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}
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| IMMVAL '-' sreg_name rel_reg swizzle
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{
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@ -1307,7 +1307,7 @@ sreg: sreg_name rel_reg swizzle
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$$.regnum = $3.regnum;
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$$.srcmod = BWRITERSPSM_COMP;
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set_rel_reg(&$$, &$4);
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$$.swizzle = $5;
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$$.u.swizzle = $5;
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}
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| IMMVAL '-' sreg_name rel_reg smod swizzle
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{
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@ -1329,7 +1329,7 @@ sreg: sreg_name rel_reg swizzle
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$$.regnum = $2.regnum;
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$$.rel_reg = NULL;
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$$.srcmod = BWRITERSPSM_NOT;
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$$.swizzle = $3;
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$$.u.swizzle = $3;
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}
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rel_reg: /* empty */
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@ -1647,7 +1647,7 @@ predicate: '(' REG_PREDICATE swizzle ')'
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$$.regnum = 0;
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$$.rel_reg = NULL;
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$$.srcmod = BWRITERSPSM_NONE;
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$$.swizzle = $3;
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$$.u.swizzle = $3;
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}
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| '(' SMOD_NOT REG_PREDICATE swizzle ')'
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{
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@ -1655,7 +1655,7 @@ predicate: '(' REG_PREDICATE swizzle ')'
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$$.regnum = 0;
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$$.rel_reg = NULL;
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$$.srcmod = BWRITERSPSM_NOT;
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$$.swizzle = $4;
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$$.u.swizzle = $4;
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}
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%%
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@ -423,7 +423,7 @@ static const char *debug_print_relarg(const struct shader_reg *reg) {
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const char *short_swizzle;
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if(!reg->rel_reg) return "";
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short_swizzle = debug_print_swizzle(reg->rel_reg->swizzle);
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short_swizzle = debug_print_swizzle(reg->rel_reg->u.swizzle);
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if(reg->rel_reg->type == BWRITERSPR_ADDR) {
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return wine_dbg_sprintf("[a%u%s]", reg->rel_reg->regnum, short_swizzle);
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@ -437,7 +437,7 @@ static const char *debug_print_relarg(const struct shader_reg *reg) {
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const char *debug_print_dstreg(const struct shader_reg *reg) {
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return wine_dbg_sprintf("%s%s%s", get_regname(reg),
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debug_print_relarg(reg),
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debug_print_writemask(reg->writemask));
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debug_print_writemask(reg->u.writemask));
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}
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const char *debug_print_srcreg(const struct shader_reg *reg) {
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@ -445,59 +445,59 @@ const char *debug_print_srcreg(const struct shader_reg *reg) {
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case BWRITERSPSM_NONE:
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return wine_dbg_sprintf("%s%s%s", get_regname(reg),
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debug_print_relarg(reg),
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debug_print_swizzle(reg->swizzle));
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debug_print_swizzle(reg->u.swizzle));
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case BWRITERSPSM_NEG:
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return wine_dbg_sprintf("-%s%s%s", get_regname(reg),
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debug_print_relarg(reg),
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debug_print_swizzle(reg->swizzle));
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debug_print_swizzle(reg->u.swizzle));
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case BWRITERSPSM_BIAS:
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return wine_dbg_sprintf("%s%s_bias%s", get_regname(reg),
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debug_print_relarg(reg),
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debug_print_swizzle(reg->swizzle));
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debug_print_swizzle(reg->u.swizzle));
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case BWRITERSPSM_BIASNEG:
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return wine_dbg_sprintf("-%s%s_bias%s", get_regname(reg),
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debug_print_relarg(reg),
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debug_print_swizzle(reg->swizzle));
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debug_print_swizzle(reg->u.swizzle));
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case BWRITERSPSM_SIGN:
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return wine_dbg_sprintf("%s%s_bx2%s", get_regname(reg),
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debug_print_relarg(reg),
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debug_print_swizzle(reg->swizzle));
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debug_print_swizzle(reg->u.swizzle));
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case BWRITERSPSM_SIGNNEG:
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return wine_dbg_sprintf("-%s%s_bx2%s", get_regname(reg),
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debug_print_relarg(reg),
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debug_print_swizzle(reg->swizzle));
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debug_print_swizzle(reg->u.swizzle));
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case BWRITERSPSM_COMP:
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return wine_dbg_sprintf("1 - %s%s%s", get_regname(reg),
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debug_print_relarg(reg),
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debug_print_swizzle(reg->swizzle));
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debug_print_swizzle(reg->u.swizzle));
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case BWRITERSPSM_X2:
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return wine_dbg_sprintf("%s%s_x2%s", get_regname(reg),
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debug_print_relarg(reg),
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debug_print_swizzle(reg->swizzle));
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debug_print_swizzle(reg->u.swizzle));
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case BWRITERSPSM_X2NEG:
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return wine_dbg_sprintf("-%s%s_x2%s", get_regname(reg),
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debug_print_relarg(reg),
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debug_print_swizzle(reg->swizzle));
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debug_print_swizzle(reg->u.swizzle));
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case BWRITERSPSM_DZ:
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return wine_dbg_sprintf("%s%s_dz%s", get_regname(reg),
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debug_print_relarg(reg),
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debug_print_swizzle(reg->swizzle));
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debug_print_swizzle(reg->u.swizzle));
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case BWRITERSPSM_DW:
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return wine_dbg_sprintf("%s%s_dw%s", get_regname(reg),
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debug_print_relarg(reg),
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debug_print_swizzle(reg->swizzle));
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debug_print_swizzle(reg->u.swizzle));
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case BWRITERSPSM_ABS:
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return wine_dbg_sprintf("%s%s_abs%s", get_regname(reg),
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debug_print_relarg(reg),
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debug_print_swizzle(reg->swizzle));
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debug_print_swizzle(reg->u.swizzle));
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case BWRITERSPSM_ABSNEG:
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return wine_dbg_sprintf("-%s%s_abs%s", get_regname(reg),
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debug_print_relarg(reg),
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debug_print_swizzle(reg->swizzle));
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debug_print_swizzle(reg->u.swizzle));
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case BWRITERSPSM_NOT:
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return wine_dbg_sprintf("!%s%s%s", get_regname(reg),
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debug_print_relarg(reg),
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debug_print_swizzle(reg->swizzle));
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debug_print_swizzle(reg->u.swizzle));
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}
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return "Unknown modifier";
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}
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@ -373,7 +373,7 @@ static void write_declarations(struct bc_writer *This,
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/* Write the dest register */
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reg.type = type;
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reg.regnum = decls[i].regnum;
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reg.writemask = decls[i].writemask;
|
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reg.u.writemask = decls[i].writemask;
|
||||
This->funcs->dstreg(This, ®, buffer, 0, decls[i].mod);
|
||||
}
|
||||
}
|
||||
|
@ -687,7 +687,7 @@ static void vs_12_dstreg(struct bc_writer *This, const struct shader_reg *reg,
|
|||
|
||||
switch(reg->type) {
|
||||
case BWRITERSPR_OUTPUT:
|
||||
token |= map_vs_output(This, reg->regnum, reg->writemask, &has_wmask);
|
||||
token |= map_vs_output(This, reg->regnum, reg->u.writemask, &has_wmask);
|
||||
break;
|
||||
|
||||
case BWRITERSPR_RASTOUT:
|
||||
|
@ -747,7 +747,7 @@ static void vs_12_dstreg(struct bc_writer *This, const struct shader_reg *reg,
|
|||
token |= d3d9_dstmod(mod);
|
||||
|
||||
if(has_wmask) {
|
||||
token |= d3d9_writemask(reg->writemask);
|
||||
token |= d3d9_writemask(reg->u.writemask);
|
||||
}
|
||||
put_dword(buffer, token);
|
||||
}
|
||||
|
@ -763,7 +763,7 @@ static void vs_1_x_srcreg(struct bc_writer *This, const struct shader_reg *reg,
|
|||
/* Map the swizzle to a writemask, the format expected
|
||||
by map_vs_output
|
||||
*/
|
||||
switch(reg->swizzle) {
|
||||
switch(reg->u.swizzle) {
|
||||
case BWRITERVS_SWIZZLE_X:
|
||||
component = BWRITERSP_WRITEMASK_0;
|
||||
break;
|
||||
|
@ -798,7 +798,7 @@ static void vs_1_x_srcreg(struct bc_writer *This, const struct shader_reg *reg,
|
|||
if(reg->rel_reg) {
|
||||
if(reg->rel_reg->type != BWRITERSPR_ADDR ||
|
||||
reg->rel_reg->regnum != 0 ||
|
||||
reg->rel_reg->swizzle != BWRITERVS_SWIZZLE_X) {
|
||||
reg->rel_reg->u.swizzle != BWRITERVS_SWIZZLE_X) {
|
||||
WARN("Relative addressing in vs_1_x is only allowed with a0.x\n");
|
||||
This->state = E_INVALIDARG;
|
||||
return;
|
||||
|
@ -813,7 +813,7 @@ static void vs_1_x_srcreg(struct bc_writer *This, const struct shader_reg *reg,
|
|||
return;
|
||||
}
|
||||
|
||||
token |= d3d9_swizzle(reg->swizzle) & D3DVS_SWIZZLE_MASK; /* already shifted */
|
||||
token |= d3d9_swizzle(reg->u.swizzle) & D3DVS_SWIZZLE_MASK; /* already shifted */
|
||||
|
||||
token |= d3d9_srcmod(reg->srcmod);
|
||||
put_dword(buffer, token);
|
||||
|
@ -908,7 +908,7 @@ static void ps_1_0123_srcreg(struct bc_writer *This, const struct shader_reg *re
|
|||
return;
|
||||
}
|
||||
|
||||
token |= d3d9_swizzle(reg->swizzle) & D3DVS_SWIZZLE_MASK; /* already shifted */
|
||||
token |= d3d9_swizzle(reg->u.swizzle) & D3DVS_SWIZZLE_MASK; /* already shifted */
|
||||
|
||||
if(reg->srcmod == BWRITERSPSM_DZ || reg->srcmod == BWRITERSPSM_DW ||
|
||||
reg->srcmod == BWRITERSPSM_ABS || reg->srcmod == BWRITERSPSM_ABSNEG ||
|
||||
|
@ -951,7 +951,7 @@ static void ps_1_0123_dstreg(struct bc_writer *This, const struct shader_reg *re
|
|||
token |= (shift << D3DSP_DSTSHIFT_SHIFT) & D3DSP_DSTSHIFT_MASK;
|
||||
token |= d3d9_dstmod(mod);
|
||||
|
||||
token |= d3d9_writemask(reg->writemask);
|
||||
token |= d3d9_writemask(reg->u.writemask);
|
||||
put_dword(buffer, token);
|
||||
}
|
||||
|
||||
|
@ -1079,17 +1079,17 @@ static void instr_ps_1_0123_texld(struct bc_writer *This,
|
|||
swizzlemask = (3 << BWRITERVS_SWIZZLE_SHIFT) |
|
||||
(3 << (BWRITERVS_SWIZZLE_SHIFT + 2)) |
|
||||
(3 << (BWRITERVS_SWIZZLE_SHIFT + 4));
|
||||
if((instr->src[0].swizzle & swizzlemask) == (BWRITERVS_X_X | BWRITERVS_Y_Y | BWRITERVS_Z_Z)) {
|
||||
if((instr->src[0].u.swizzle & swizzlemask) == (BWRITERVS_X_X | BWRITERVS_Y_Y | BWRITERVS_Z_Z)) {
|
||||
TRACE("writing texreg2rgb\n");
|
||||
This->funcs->opcode(This, instr, D3DSIO_TEXREG2RGB & D3DSI_OPCODE_MASK, buffer);
|
||||
} else if(instr->src[0].swizzle == (BWRITERVS_X_W | BWRITERVS_Y_X | BWRITERVS_Z_X | BWRITERVS_W_X)) {
|
||||
} else if(instr->src[0].u.swizzle == (BWRITERVS_X_W | BWRITERVS_Y_X | BWRITERVS_Z_X | BWRITERVS_W_X)) {
|
||||
TRACE("writing texreg2ar\n");
|
||||
This->funcs->opcode(This, instr, D3DSIO_TEXREG2AR & D3DSI_OPCODE_MASK, buffer);
|
||||
} else if(instr->src[0].swizzle == (BWRITERVS_X_Y | BWRITERVS_Y_Z | BWRITERVS_Z_Z | BWRITERVS_W_Z)) {
|
||||
} else if(instr->src[0].u.swizzle == (BWRITERVS_X_Y | BWRITERVS_Y_Z | BWRITERVS_Z_Z | BWRITERVS_W_Z)) {
|
||||
TRACE("writing texreg2gb\n");
|
||||
This->funcs->opcode(This, instr, D3DSIO_TEXREG2GB & D3DSI_OPCODE_MASK, buffer);
|
||||
} else {
|
||||
WARN("Unsupported src addr swizzle in dependent texld: 0x%08x\n", instr->src[0].swizzle);
|
||||
WARN("Unsupported src addr swizzle in dependent texld: 0x%08x\n", instr->src[0].u.swizzle);
|
||||
This->state = E_INVALIDARG;
|
||||
return;
|
||||
}
|
||||
|
@ -1100,7 +1100,7 @@ static void instr_ps_1_0123_texld(struct bc_writer *This,
|
|||
*/
|
||||
This->funcs->dstreg(This, &instr->dst, buffer, instr->shift, instr->dstmod);
|
||||
reg = instr->src[0];
|
||||
reg.swizzle = BWRITERVS_NOSWIZZLE;
|
||||
reg.u.swizzle = BWRITERVS_NOSWIZZLE;
|
||||
This->funcs->srcreg(This, ®, buffer);
|
||||
} else {
|
||||
WARN("Invalid address data source register\n");
|
||||
|
@ -1211,7 +1211,7 @@ static void ps_1_4_srcreg(struct bc_writer *This, const struct shader_reg *reg,
|
|||
return;
|
||||
}
|
||||
|
||||
token |= d3d9_swizzle(reg->swizzle) & D3DVS_SWIZZLE_MASK; /* already shifted */
|
||||
token |= d3d9_swizzle(reg->u.swizzle) & D3DVS_SWIZZLE_MASK; /* already shifted */
|
||||
|
||||
if(reg->srcmod == BWRITERSPSM_ABS || reg->srcmod == BWRITERSPSM_ABSNEG ||
|
||||
reg->srcmod == BWRITERSPSM_NOT) {
|
||||
|
@ -1254,7 +1254,7 @@ static void ps_1_4_dstreg(struct bc_writer *This, const struct shader_reg *reg,
|
|||
token |= (shift << D3DSP_DSTSHIFT_SHIFT) & D3DSP_DSTSHIFT_MASK;
|
||||
token |= d3d9_dstmod(mod);
|
||||
|
||||
token |= d3d9_writemask(reg->writemask);
|
||||
token |= d3d9_writemask(reg->u.writemask);
|
||||
put_dword(buffer, token);
|
||||
}
|
||||
|
||||
|
@ -1388,7 +1388,7 @@ static void vs_2_srcreg(struct bc_writer *This,
|
|||
/* Map the swizzle to a writemask, the format expected
|
||||
by map_vs_output
|
||||
*/
|
||||
switch(reg->swizzle) {
|
||||
switch(reg->u.swizzle) {
|
||||
case BWRITERVS_SWIZZLE_X:
|
||||
component = BWRITERSP_WRITEMASK_0;
|
||||
break;
|
||||
|
@ -1461,7 +1461,7 @@ static void vs_2_srcreg(struct bc_writer *This,
|
|||
return;
|
||||
}
|
||||
|
||||
token |= d3d9_swizzle(reg->swizzle) & D3DVS_SWIZZLE_MASK; /* already shifted */
|
||||
token |= d3d9_swizzle(reg->u.swizzle) & D3DVS_SWIZZLE_MASK; /* already shifted */
|
||||
|
||||
token |= d3d9_srcmod(reg->srcmod);
|
||||
|
||||
|
@ -1706,7 +1706,7 @@ static void ps_2_srcreg(struct bc_writer *This,
|
|||
return;
|
||||
}
|
||||
|
||||
token |= d3d9_swizzle(reg->swizzle) & D3DVS_SWIZZLE_MASK; /* already shifted */
|
||||
token |= d3d9_swizzle(reg->u.swizzle) & D3DVS_SWIZZLE_MASK; /* already shifted */
|
||||
|
||||
token |= d3d9_srcmod(reg->srcmod);
|
||||
put_dword(buffer, token);
|
||||
|
@ -1759,7 +1759,7 @@ static void ps_2_0_dstreg(struct bc_writer *This,
|
|||
token |= (shift << D3DSP_DSTSHIFT_SHIFT) & D3DSP_DSTSHIFT_MASK;
|
||||
token |= d3d9_dstmod(mod);
|
||||
|
||||
token |= d3d9_writemask(reg->writemask);
|
||||
token |= d3d9_writemask(reg->u.writemask);
|
||||
put_dword(buffer, token);
|
||||
}
|
||||
|
||||
|
@ -1905,7 +1905,7 @@ static void sm_3_srcreg(struct bc_writer *This,
|
|||
token |= (d3d9reg << D3DSP_REGTYPE_SHIFT2) & D3DSP_REGTYPE_MASK2;
|
||||
token |= reg->regnum & D3DSP_REGNUM_MASK;
|
||||
|
||||
token |= d3d9_swizzle(reg->swizzle) & D3DVS_SWIZZLE_MASK;
|
||||
token |= d3d9_swizzle(reg->u.swizzle) & D3DVS_SWIZZLE_MASK;
|
||||
token |= d3d9_srcmod(reg->srcmod);
|
||||
|
||||
if(reg->rel_reg) {
|
||||
|
@ -1960,7 +1960,7 @@ static void sm_3_dstreg(struct bc_writer *This,
|
|||
|
||||
token |= d3d9_dstmod(mod);
|
||||
|
||||
token |= d3d9_writemask(reg->writemask);
|
||||
token |= d3d9_writemask(reg->u.writemask);
|
||||
put_dword(buffer, token);
|
||||
|
||||
/* vs_2_0 and newer write the register containing the index explicitly in the
|
||||
|
|
|
@ -83,7 +83,7 @@ struct shader_reg {
|
|||
union {
|
||||
DWORD swizzle;
|
||||
DWORD writemask;
|
||||
};
|
||||
} u;
|
||||
};
|
||||
|
||||
struct instruction {
|
||||
|
|
Loading…
Reference in New Issue