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d3dx9: Support some more vs_3_0 instructions in the shader assembler.

This commit is contained in:
Matteo Bruni 2010-05-05 20:21:10 +02:00 committed by Alexandre Julliard
parent 399bde576e
commit fb3ee6e0a6
6 changed files with 402 additions and 11 deletions
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37
dlls/d3dx9_36/asmshader.l
View File

@ -85,7 +85,44 @@ ANY (.)
%%
/* Common instructions(vertex and pixel shaders) */
add {return INSTR_ADD; }
nop {return INSTR_NOP; }
mov {return INSTR_MOV; }
sub {return INSTR_SUB; }
mad {return INSTR_MAD; }
mul {return INSTR_MUL; }
rcp {return INSTR_RCP; }
rsq {return INSTR_RSQ; }
dp3 {return INSTR_DP3; }
dp4 {return INSTR_DP4; }
min {return INSTR_MIN; }
max {return INSTR_MAX; }
slt {return INSTR_SLT; }
sge {return INSTR_SGE; }
abs {return INSTR_ABS; }
exp {return INSTR_EXP; }
log {return INSTR_LOG; }
expp {return INSTR_EXPP; }
logp {return INSTR_LOGP; }
dst {return INSTR_DST; }
lrp {return INSTR_LRP; }
frc {return INSTR_FRC; }
pow {return INSTR_POW; }
crs {return INSTR_CRS; }
sgn {return INSTR_SGN; }
nrm {return INSTR_NRM; }
sincos {return INSTR_SINCOS; }
m4x4 {return INSTR_M4x4; }
m4x3 {return INSTR_M4x3; }
m3x4 {return INSTR_M3x4; }
m3x3 {return INSTR_M3x3; }
m3x2 {return INSTR_M3x2; }
texldl {return INSTR_TEXLDL; }
/* Vertex shader only instructions */
lit {return INSTR_LIT; }
mova {return INSTR_MOVA; }
{REG_TEMP} {
asmshader_lval.regnum = atoi(yytext + 1);

208
dlls/d3dx9_36/asmshader.y
View File

@ -84,7 +84,43 @@ void set_rel_reg(struct shader_reg *reg, struct rel_reg *rel) {
}
/* Common instructions between vertex and pixel shaders */
%token INSTR_ADD
%token INSTR_NOP
%token INSTR_MOV
%token INSTR_SUB
%token INSTR_MAD
%token INSTR_MUL
%token INSTR_RCP
%token INSTR_RSQ
%token INSTR_DP3
%token INSTR_DP4
%token INSTR_MIN
%token INSTR_MAX
%token INSTR_SLT
%token INSTR_SGE
%token INSTR_ABS
%token INSTR_EXP
%token INSTR_LOG
%token INSTR_EXPP
%token INSTR_LOGP
%token INSTR_DST
%token INSTR_LRP
%token INSTR_FRC
%token INSTR_POW
%token INSTR_CRS
%token INSTR_SGN
%token INSTR_NRM
%token INSTR_SINCOS
%token INSTR_M4x4
%token INSTR_M4x3
%token INSTR_M3x4
%token INSTR_M3x3
%token INSTR_M3x2
%token INSTR_TEXLDL
/* Vertex shader only instructions */
%token INSTR_LIT
%token INSTR_MOVA
/* Registers */
%token <regnum> REG_TEMP
@ -249,11 +285,181 @@ complexinstr: instruction
}
instruction: INSTR_MOV omods dreg ',' sregs
instruction: INSTR_ADD omods dreg ',' sregs
{
TRACE("ADD\n");
asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_ADD, $2.mod, $2.shift, 0, &$3, &$5, 2);
}
| INSTR_NOP
{
TRACE("NOP\n");
asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_NOP, 0, 0, 0, 0, 0, 0);
}
| INSTR_MOV omods dreg ',' sregs
{
TRACE("MOV\n");
asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_MOV, $2.mod, $2.shift, 0, &$3, &$5, 1);
}
| INSTR_SUB omods dreg ',' sregs
{
TRACE("SUB\n");
asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_SUB, $2.mod, $2.shift, 0, &$3, &$5, 2);
}
| INSTR_MAD omods dreg ',' sregs
{
TRACE("MAD\n");
asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_MAD, $2.mod, $2.shift, 0, &$3, &$5, 3);
}
| INSTR_MUL omods dreg ',' sregs
{
TRACE("MUL\n");
asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_MUL, $2.mod, $2.shift, 0, &$3, &$5, 2);
}
| INSTR_RCP omods dreg ',' sregs
{
TRACE("RCP\n");
asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_RCP, $2.mod, $2.shift, 0, &$3, &$5, 1);
}
| INSTR_RSQ omods dreg ',' sregs
{
TRACE("RSQ\n");
asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_RSQ, $2.mod, $2.shift, 0, &$3, &$5, 1);
}
| INSTR_DP3 omods dreg ',' sregs
{
TRACE("DP3\n");
asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_DP3, $2.mod, $2.shift, 0, &$3, &$5, 2);
}
| INSTR_DP4 omods dreg ',' sregs
{
TRACE("DP4\n");
asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_DP4, $2.mod, $2.shift, 0, &$3, &$5, 2);
}
| INSTR_MIN omods dreg ',' sregs
{
TRACE("MIN\n");
asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_MIN, $2.mod, $2.shift, 0, &$3, &$5, 2);
}
| INSTR_MAX omods dreg ',' sregs
{
TRACE("MAX\n");
asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_MAX, $2.mod, $2.shift, 0, &$3, &$5, 2);
}
| INSTR_SLT omods dreg ',' sregs
{
TRACE("SLT\n");
asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_SLT, $2.mod, $2.shift, 0, &$3, &$5, 2);
}
| INSTR_SGE omods dreg ',' sregs
{
TRACE("SGE\n");
asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_SGE, $2.mod, $2.shift, 0, &$3, &$5, 2);
}
| INSTR_ABS omods dreg ',' sregs
{
TRACE("ABS\n");
asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_ABS, $2.mod, $2.shift, 0, &$3, &$5, 1);
}
| INSTR_EXP omods dreg ',' sregs
{
TRACE("EXP\n");
asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_EXP, $2.mod, $2.shift, 0, &$3, &$5, 1);
}
| INSTR_LOG omods dreg ',' sregs
{
TRACE("LOG\n");
asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_LOG, $2.mod, $2.shift, 0, &$3, &$5, 1);
}
| INSTR_LOGP omods dreg ',' sregs
{
TRACE("LOGP\n");
asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_LOGP, $2.mod, $2.shift, 0, &$3, &$5, 1);
}
| INSTR_EXPP omods dreg ',' sregs
{
TRACE("EXPP\n");
asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_EXPP, $2.mod, $2.shift, 0, &$3, &$5, 1);
}
| INSTR_DST omods dreg ',' sregs
{
TRACE("DST\n");
asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_DST, $2.mod, $2.shift, 0, &$3, &$5, 2);
}
| INSTR_LRP omods dreg ',' sregs
{
TRACE("LRP\n");
asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_LRP, $2.mod, $2.shift, 0, &$3, &$5, 3);
}
| INSTR_FRC omods dreg ',' sregs
{
TRACE("FRC\n");
asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_FRC, $2.mod, $2.shift, 0, &$3, &$5, 1);
}
| INSTR_POW omods dreg ',' sregs
{
TRACE("POW\n");
asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_POW, $2.mod, $2.shift, 0, &$3, &$5, 2);
}
| INSTR_CRS omods dreg ',' sregs
{
TRACE("CRS\n");
asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_CRS, $2.mod, $2.shift, 0, &$3, &$5, 2);
}
| INSTR_SGN omods dreg ',' sregs
{
TRACE("SGN\n");
asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_SGN, $2.mod, $2.shift, 0, &$3, &$5, 3);
}
| INSTR_NRM omods dreg ',' sregs
{
TRACE("NRM\n");
asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_NRM, $2.mod, $2.shift, 0, &$3, &$5, 1);
}
| INSTR_SINCOS omods dreg ',' sregs
{
TRACE("SINCOS\n");
asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_SINCOS, $2.mod, $2.shift, 0, &$3, &$5, 1);
}
| INSTR_M4x4 omods dreg ',' sregs
{
TRACE("M4x4\n");
asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_M4x4, $2.mod, $2.shift, 0, &$3, &$5, 2);
}
| INSTR_M4x3 omods dreg ',' sregs
{
TRACE("M4x3\n");
asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_M4x3, $2.mod, $2.shift, 0, &$3, &$5, 2);
}
| INSTR_M3x4 omods dreg ',' sregs
{
TRACE("M3x4\n");
asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_M3x4, $2.mod, $2.shift, 0, &$3, &$5, 2);
}
| INSTR_M3x3 omods dreg ',' sregs
{
TRACE("M3x3\n");
asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_M3x3, $2.mod, $2.shift, 0, &$3, &$5, 2);
}
| INSTR_M3x2 omods dreg ',' sregs
{
TRACE("M3x2\n");
asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_M3x2, $2.mod, $2.shift, 0, &$3, &$5, 2);
}
| INSTR_TEXLDL omods dreg ',' sregs
{
TRACE("TEXLDL\n");
asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_TEXLDL, $2.mod, $2.shift, 0, &$3, &$5, 2);
}
| INSTR_LIT omods dreg ',' sregs
{
TRACE("LIT\n");
asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_LIT, $2.mod, $2.shift, 0, &$3, &$5, 1);
}
| INSTR_MOVA omods dreg ',' sregs
{
TRACE("MOVA\n");
asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_MOVA, $2.mod, $2.shift, 0, &$3, &$5, 1);
}
dreg: dreg_name rel_reg
{

68
dlls/d3dx9_36/asmutils.c
View File

@ -116,7 +116,41 @@ DWORD d3d9_register(DWORD bwriter_register) {
DWORD d3d9_opcode(DWORD bwriter_opcode) {
switch(bwriter_opcode) {
case BWRITERSIO_NOP: return D3DSIO_NOP;
case BWRITERSIO_MOV: return D3DSIO_MOV;
case BWRITERSIO_ADD: return D3DSIO_ADD;
case BWRITERSIO_SUB: return D3DSIO_SUB;
case BWRITERSIO_MAD: return D3DSIO_MAD;
case BWRITERSIO_MUL: return D3DSIO_MUL;
case BWRITERSIO_RCP: return D3DSIO_RCP;
case BWRITERSIO_RSQ: return D3DSIO_RSQ;
case BWRITERSIO_DP3: return D3DSIO_DP3;
case BWRITERSIO_DP4: return D3DSIO_DP4;
case BWRITERSIO_MIN: return D3DSIO_MIN;
case BWRITERSIO_MAX: return D3DSIO_MAX;
case BWRITERSIO_SLT: return D3DSIO_SLT;
case BWRITERSIO_SGE: return D3DSIO_SGE;
case BWRITERSIO_EXP: return D3DSIO_EXP;
case BWRITERSIO_LOG: return D3DSIO_LOG;
case BWRITERSIO_LIT: return D3DSIO_LIT;
case BWRITERSIO_DST: return D3DSIO_DST;
case BWRITERSIO_LRP: return D3DSIO_LRP;
case BWRITERSIO_FRC: return D3DSIO_FRC;
case BWRITERSIO_M4x4: return D3DSIO_M4x4;
case BWRITERSIO_M4x3: return D3DSIO_M4x3;
case BWRITERSIO_M3x4: return D3DSIO_M3x4;
case BWRITERSIO_M3x3: return D3DSIO_M3x3;
case BWRITERSIO_M3x2: return D3DSIO_M3x2;
case BWRITERSIO_POW: return D3DSIO_POW;
case BWRITERSIO_CRS: return D3DSIO_CRS;
case BWRITERSIO_SGN: return D3DSIO_SGN;
case BWRITERSIO_ABS: return D3DSIO_ABS;
case BWRITERSIO_NRM: return D3DSIO_NRM;
case BWRITERSIO_SINCOS: return D3DSIO_SINCOS;
case BWRITERSIO_MOVA: return D3DSIO_MOVA;
case BWRITERSIO_EXPP: return D3DSIO_EXPP;
case BWRITERSIO_LOGP: return D3DSIO_LOGP;
case BWRITERSIO_TEXLDL: return D3DSIO_TEXLDL;
case BWRITERSIO_COMMENT: return D3DSIO_COMMENT;
case BWRITERSIO_END: return D3DSIO_END;
@ -312,7 +346,41 @@ const char *debug_print_srcreg(const struct shader_reg *reg, shader_type st) {
const char *debug_print_opcode(DWORD opcode) {
switch(opcode){
case BWRITERSIO_NOP: return "nop";
case BWRITERSIO_MOV: return "mov";
case BWRITERSIO_ADD: return "add";
case BWRITERSIO_SUB: return "sub";
case BWRITERSIO_MAD: return "mad";
case BWRITERSIO_MUL: return "mul";
case BWRITERSIO_RCP: return "rcp";
case BWRITERSIO_RSQ: return "rsq";
case BWRITERSIO_DP3: return "dp3";
case BWRITERSIO_DP4: return "dp4";
case BWRITERSIO_MIN: return "min";
case BWRITERSIO_MAX: return "max";
case BWRITERSIO_SLT: return "slt";
case BWRITERSIO_SGE: return "sge";
case BWRITERSIO_EXP: return "exp";
case BWRITERSIO_LOG: return "log";
case BWRITERSIO_LIT: return "lit";
case BWRITERSIO_DST: return "dst";
case BWRITERSIO_LRP: return "lrp";
case BWRITERSIO_FRC: return "frc";
case BWRITERSIO_M4x4: return "m4x4";
case BWRITERSIO_M4x3: return "m4x3";
case BWRITERSIO_M3x4: return "m3x4";
case BWRITERSIO_M3x3: return "m3x3";
case BWRITERSIO_M3x2: return "m3x2";
case BWRITERSIO_POW: return "pow";
case BWRITERSIO_CRS: return "crs";
case BWRITERSIO_SGN: return "sgn";
case BWRITERSIO_ABS: return "abs";
case BWRITERSIO_NRM: return "nrm";
case BWRITERSIO_SINCOS: return "sincos";
case BWRITERSIO_MOVA: return "mova";
case BWRITERSIO_EXPP: return "expp";
case BWRITERSIO_LOGP: return "logp";
case BWRITERSIO_TEXLDL: return "texldl";
default: return "unknown";
}

36
dlls/d3dx9_36/bytecodewriter.c
View File

@ -283,7 +283,43 @@ static void sm_3_dstreg(struct bc_writer *This,
}
static const struct instr_handler_table vs_3_handlers[] = {
{BWRITERSIO_ADD, instr_handler},
{BWRITERSIO_NOP, instr_handler},
{BWRITERSIO_MOV, instr_handler},
{BWRITERSIO_SUB, instr_handler},
{BWRITERSIO_MAD, instr_handler},
{BWRITERSIO_MUL, instr_handler},
{BWRITERSIO_RCP, instr_handler},
{BWRITERSIO_RSQ, instr_handler},
{BWRITERSIO_DP3, instr_handler},
{BWRITERSIO_DP4, instr_handler},
{BWRITERSIO_MIN, instr_handler},
{BWRITERSIO_MAX, instr_handler},
{BWRITERSIO_SLT, instr_handler},
{BWRITERSIO_SGE, instr_handler},
{BWRITERSIO_ABS, instr_handler},
{BWRITERSIO_EXP, instr_handler},
{BWRITERSIO_LOG, instr_handler},
{BWRITERSIO_EXPP, instr_handler},
{BWRITERSIO_LOGP, instr_handler},
{BWRITERSIO_DST, instr_handler},
{BWRITERSIO_LRP, instr_handler},
{BWRITERSIO_FRC, instr_handler},
{BWRITERSIO_CRS, instr_handler},
{BWRITERSIO_SGN, instr_handler},
{BWRITERSIO_NRM, instr_handler},
{BWRITERSIO_SINCOS, instr_handler},
{BWRITERSIO_M4x4, instr_handler},
{BWRITERSIO_M4x3, instr_handler},
{BWRITERSIO_M3x4, instr_handler},
{BWRITERSIO_M3x3, instr_handler},
{BWRITERSIO_M3x2, instr_handler},
{BWRITERSIO_LIT, instr_handler},
{BWRITERSIO_POW, instr_handler},
{BWRITERSIO_MOVA, instr_handler},
{BWRITERSIO_TEXLDL, instr_handler},
{BWRITERSIO_END, NULL},
};

41
dlls/d3dx9_36/d3dx9_36_private.h
View File

@ -363,10 +363,45 @@ DWORD d3d9_opcode(DWORD bwriter_opcode);
intermediate representation
*/
typedef enum _BWRITERSHADER_INSTRUCTION_OPCODE_TYPE {
BWRITERSIO_MOV = 1,
BWRITERSIO_NOP,
BWRITERSIO_MOV,
BWRITERSIO_ADD,
BWRITERSIO_SUB,
BWRITERSIO_MAD,
BWRITERSIO_MUL,
BWRITERSIO_RCP,
BWRITERSIO_RSQ,
BWRITERSIO_DP3,
BWRITERSIO_DP4,
BWRITERSIO_MIN,
BWRITERSIO_MAX,
BWRITERSIO_SLT,
BWRITERSIO_SGE,
BWRITERSIO_EXP,
BWRITERSIO_LOG,
BWRITERSIO_LIT,
BWRITERSIO_DST,
BWRITERSIO_LRP,
BWRITERSIO_FRC,
BWRITERSIO_M4x4,
BWRITERSIO_M4x3,
BWRITERSIO_M3x4,
BWRITERSIO_M3x3,
BWRITERSIO_M3x2,
BWRITERSIO_POW,
BWRITERSIO_CRS,
BWRITERSIO_SGN,
BWRITERSIO_ABS,
BWRITERSIO_NRM,
BWRITERSIO_SINCOS,
BWRITERSIO_MOVA,
BWRITERSIO_COMMENT = 0xfffe,
BWRITERSIO_END = 0Xffff,
BWRITERSIO_EXPP,
BWRITERSIO_LOGP,
BWRITERSIO_TEXLDL,
BWRITERSIO_COMMENT,
BWRITERSIO_END,
} BWRITERSHADER_INSTRUCTION_OPCODE_TYPE;
typedef enum _BWRITERSHADER_PARAM_REGISTER_TYPE {

23
dlls/d3dx9_36/tests/asm.c
View File

@ -1033,11 +1033,11 @@ static void vs_3_0_test(void) {
"dcl_texcoord12 o11\n",
{0xfffe0300, 0x0200001f, 0x800c0005, 0xe00f000b, 0x0000ffff}
},*/
/* {*/ /* shader 4 */
/* "vs_3_0\n"
{ /* shader 4 */
"vs_3_0\n"
"texldl r0, v0, s0\n",
{0xfffe0300, 0x0300005f, 0x800f0000, 0x90e40000, 0xa0e40800, 0x0000ffff}
},*/
},
{ /* shader 5 */
"vs_3_0\n"
"mov r0, c0[aL]\n",
@ -1048,11 +1048,11 @@ static void vs_3_0_test(void) {
"mov o[ a0.x + 12 ], r0\n",
{0xfffe0300, 0x03000001, 0xe00f200c, 0xb0000000, 0x80e40000, 0x0000ffff}
},
/* {*/ /* shader 7 */
/* "vs_3_0\n"
{ /* shader 7 */
"vs_3_0\n"
"add_sat r0, r0, r1\n",
{0xfffe0300, 0x03000002, 0x801f0000, 0x80e40000, 0x80e40001, 0x0000ffff}
},*/
},
{ /* shader 8 */
"vs_3_0\n"
"mov r2, r1_abs\n",
@ -1068,7 +1068,16 @@ static void vs_3_0_test(void) {
"mov r2.xyb, r1\n",
{0xfffe0300, 0x02000001, 0x80070002, 0x80e40001, 0x0000ffff}
},
{ /* shader 11 */
"vs_3_0\n"
"mova_sat a0.x, r1\n",
{0xfffe0300, 0x0200002e, 0xb0110000, 0x80e40001, 0x0000ffff}
},
{ /* shader 12 */
"vs_3_0\n"
"sincos r0, r1\n",
{0xfffe0300, 0x02000025, 0x800f0000, 0x80e40001, 0x0000ffff}
},
};
exec_tests("vs_3_0", tests, sizeof(tests) / sizeof(tests[0]));