wined3d: Implement SM5 imm_atomic_alloc instruction.
Signed-off-by: Józef Kucia <jkucia@codeweavers.com> Signed-off-by: Henri Verbeet <hverbeet@codeweavers.com> Signed-off-by: Alexandre Julliard <julliard@winehq.org>
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@ -2225,6 +2225,10 @@ static void shader_generate_glsl_declarations(const struct wined3d_context *cont
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else
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else
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shader_addline(buffer, "writeonly uniform %s%s %s_image%u;\n",
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shader_addline(buffer, "writeonly uniform %s%s %s_image%u;\n",
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image_type_prefix, image_type, prefix, i);
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image_type_prefix, image_type, prefix, i);
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if (reg_maps->uav_counter_mask & (1u << i))
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shader_addline(buffer, "layout(binding = %u) uniform atomic_uint %s_counter%u;\n",
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i, prefix, i);
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}
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}
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/* Declare uniforms for NP2 texcoord fixup:
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/* Declare uniforms for NP2 texcoord fixup:
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@ -5145,6 +5149,15 @@ static void shader_glsl_atomic(const struct wined3d_shader_instruction *ins)
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string_buffer_release(priv->string_buffers, address);
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string_buffer_release(priv->string_buffers, address);
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}
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}
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static void shader_glsl_uav_counter(const struct wined3d_shader_instruction *ins)
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{
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const char *prefix = shader_glsl_get_prefix(ins->ctx->reg_maps->shader_version.type);
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shader_glsl_append_dst(ins->ctx->buffer, ins);
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shader_addline(ins->ctx->buffer, "atomicCounterIncrement(%s_counter%u));\n",
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prefix, ins->src[0].reg.idx[0].offset);
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}
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static void shader_glsl_ld_uav(const struct wined3d_shader_instruction *ins)
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static void shader_glsl_ld_uav(const struct wined3d_shader_instruction *ins)
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{
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{
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const struct wined3d_shader_reg_maps *reg_maps = ins->ctx->reg_maps;
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const struct wined3d_shader_reg_maps *reg_maps = ins->ctx->reg_maps;
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@ -9637,7 +9650,7 @@ static const SHADER_HANDLER shader_glsl_instruction_handler_table[WINED3DSIH_TAB
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/* WINED3DSIH_IMAD */ shader_glsl_mad,
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/* WINED3DSIH_IMAD */ shader_glsl_mad,
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/* WINED3DSIH_IMAX */ shader_glsl_map2gl,
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/* WINED3DSIH_IMAX */ shader_glsl_map2gl,
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/* WINED3DSIH_IMIN */ shader_glsl_map2gl,
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/* WINED3DSIH_IMIN */ shader_glsl_map2gl,
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/* WINED3DSIH_IMM_ATOMIC_ALLOC */ NULL,
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/* WINED3DSIH_IMM_ATOMIC_ALLOC */ shader_glsl_uav_counter,
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/* WINED3DSIH_IMM_ATOMIC_AND */ shader_glsl_atomic,
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/* WINED3DSIH_IMM_ATOMIC_AND */ shader_glsl_atomic,
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/* WINED3DSIH_IMM_ATOMIC_CMP_EXCH */ shader_glsl_atomic,
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/* WINED3DSIH_IMM_ATOMIC_CMP_EXCH */ shader_glsl_atomic,
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/* WINED3DSIH_IMM_ATOMIC_CONSUME */ NULL,
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/* WINED3DSIH_IMM_ATOMIC_CONSUME */ NULL,
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@ -1370,7 +1370,17 @@ static HRESULT shader_get_registers_used(struct wined3d_shader *shader, const st
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}
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}
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}
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}
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if ((WINED3DSIH_ATOMIC_AND <= ins.handler_idx && ins.handler_idx <= WINED3DSIH_ATOMIC_XOR)
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if (ins.handler_idx == WINED3DSIH_IMM_ATOMIC_ALLOC)
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{
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unsigned int reg_idx = ins.src[0].reg.idx[0].offset;
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if (reg_idx >= MAX_UNORDERED_ACCESS_VIEWS)
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{
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ERR("Invalid UAV index %u.\n", reg_idx);
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break;
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}
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reg_maps->uav_counter_mask |= (1u << reg_idx);
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}
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else if ((WINED3DSIH_ATOMIC_AND <= ins.handler_idx && ins.handler_idx <= WINED3DSIH_ATOMIC_XOR)
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|| (WINED3DSIH_IMM_ATOMIC_AND <= ins.handler_idx
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|| (WINED3DSIH_IMM_ATOMIC_AND <= ins.handler_idx
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&& ins.handler_idx <= WINED3DSIH_IMM_ATOMIC_XOR
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&& ins.handler_idx <= WINED3DSIH_IMM_ATOMIC_XOR
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&& ins.handler_idx != WINED3DSIH_IMM_ATOMIC_CONSUME)
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&& ins.handler_idx != WINED3DSIH_IMM_ATOMIC_CONSUME)
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@ -896,6 +896,7 @@ struct wined3d_shader_reg_maps
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BYTE luminanceparams; /* MAX_TEXTURES, 8 */
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BYTE luminanceparams; /* MAX_TEXTURES, 8 */
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struct wined3d_shader_resource_info uav_resource_info[MAX_UNORDERED_ACCESS_VIEWS];
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struct wined3d_shader_resource_info uav_resource_info[MAX_UNORDERED_ACCESS_VIEWS];
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DWORD uav_read_mask; /* MAX_UNORDERED_ACCESS_VIEWS, 8 */
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DWORD uav_read_mask; /* MAX_UNORDERED_ACCESS_VIEWS, 8 */
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DWORD uav_counter_mask; /* MAX_UNORDERED_ACCESS_VIEWS, 8 */
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WORD usesnrm : 1;
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WORD usesnrm : 1;
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WORD vpos : 1;
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WORD vpos : 1;
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