winedbg: Disassemble more Thumb instructions.
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83761d20a8
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@ -70,6 +70,11 @@ static char const tbl_hiops_t[][4] = {
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"add", "cmp", "mov", "bx"
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"add", "cmp", "mov", "bx"
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};
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};
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static char const tbl_aluops_t[][4] = {
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"and", "eor", "lsl", "lsr", "asr", "adc", "sbc", "ror", "tst", "neg", "cmp", "cmn", "orr",
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"mul", "bic", "mvn"
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};
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static char const tbl_immops_t[][4] = {
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static char const tbl_immops_t[][4] = {
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"mov", "cmp", "add", "sub"
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"mov", "cmp", "add", "sub"
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};
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};
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@ -335,6 +340,17 @@ static WORD thumb_disasm_hireg(WORD inst, ADDRESS64 *addr)
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return 0;
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return 0;
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}
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}
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static WORD thumb_disasm_aluop(WORD inst, ADDRESS64 *addr)
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{
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short dst = inst & 0x07;
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short src = (inst >> 3) & 0x07;
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short op = (inst >> 6) & 0x0f;
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dbg_printf("\n\t%s\t%s, %s", tbl_aluops_t[op], tbl_regs[dst], tbl_regs[src]);
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return 0;
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}
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static WORD thumb_disasm_blocktrans(WORD inst, ADDRESS64 *addr)
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static WORD thumb_disasm_blocktrans(WORD inst, ADDRESS64 *addr)
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{
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{
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short lrpc = (inst >> 8) & 0x01;
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short lrpc = (inst >> 8) & 0x01;
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@ -371,7 +387,14 @@ static WORD thumb_disasm_longbl(WORD inst, ADDRESS64 *addr)
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if (!((inst2 & 0xf800) == 0xf800)) return inst;
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if (!((inst2 & 0xf800) == 0xf800)) return inst;
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offset += (inst2 & 0x07ff) << 1;
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offset += (inst2 & 0x07ff) << 1;
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dbg_printf("\tbl\t%08x", offset);
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dbg_printf("\n\tbl\t%08x", offset);
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return 0;
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}
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static WORD thumb_disasm_condbranch(WORD inst, ADDRESS64 *addr)
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{
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WORD offset = inst & 0x00ff;
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dbg_printf("\n\tb%s\t%04x", tbl_cond[(inst >> 8) & 0x0f], offset);
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return 0;
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return 0;
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}
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}
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@ -402,6 +425,16 @@ static WORD thumb_disasm_ldrsprel(WORD inst, ADDRESS64 *addr)
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return 0;
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return 0;
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}
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}
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static WORD thumb_disasm_addsprel(WORD inst, ADDRESS64 *addr)
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{
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WORD offset = (inst & 0x7f) << 2;
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if ((inst >> 7) & 0x01)
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dbg_printf("\n\tsub\tsp, sp, #%u", offset);
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else
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dbg_printf("\n\tadd\tsp, sp, #%u", offset);
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return 0;
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}
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static WORD thumb_disasm_ldrimm(WORD inst, ADDRESS64 *addr)
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static WORD thumb_disasm_ldrimm(WORD inst, ADDRESS64 *addr)
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{
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{
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WORD offset = (inst & 0x07c0) >> 6;
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WORD offset = (inst & 0x07c0) >> 6;
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@ -417,6 +450,28 @@ static WORD thumb_disasm_immop(WORD inst, ADDRESS64 *addr)
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return 0;
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return 0;
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}
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}
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static WORD thumb_disasm_addsub(WORD inst, ADDRESS64 *addr)
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{
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WORD op = (inst >> 9) & 0x01;
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WORD immediate = (inst >> 10) & 0x01;
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dbg_printf("\n\t%s\t%s, %s, ", op ? "sub" : "add",
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tbl_regs[inst & 0x07], tbl_regs[(inst >> 3) & 0x07]);
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if (immediate)
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dbg_printf("#%d", (inst >> 6) & 0x07);
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else
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dbg_printf("%s", tbl_regs[(inst >> 6) & 0x07]);
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return 0;
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}
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static WORD thumb_disasm_movshift(WORD inst, ADDRESS64 *addr)
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{
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WORD op = (inst >> 11) & 0x03;
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dbg_printf("\n\t%s\t%s, %s, #%u", tbl_shifts[op],
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tbl_regs[inst & 0x07], tbl_regs[(inst >> 3) & 0x07], (inst >> 6) & 0x1f);
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return 0;
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}
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struct inst_arm
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struct inst_arm
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{
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{
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UINT mask;
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UINT mask;
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@ -447,14 +502,20 @@ struct inst_thumb16
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static const struct inst_thumb16 tbl_thumb16[] = {
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static const struct inst_thumb16 tbl_thumb16[] = {
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{ 0xfc00, 0x4400, thumb_disasm_hireg },
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{ 0xfc00, 0x4400, thumb_disasm_hireg },
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{ 0xfc00, 0x4000, thumb_disasm_aluop },
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{ 0xf600, 0xb400, thumb_disasm_blocktrans },
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{ 0xf600, 0xb400, thumb_disasm_blocktrans },
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{ 0xf800, 0xf000, thumb_disasm_longbl },
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{ 0xf800, 0xf000, thumb_disasm_longbl },
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{ 0xf000, 0xd000, thumb_disasm_condbranch },
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{ 0xf800, 0x4800, thumb_disasm_ldrpcrel },
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{ 0xf800, 0x4800, thumb_disasm_ldrpcrel },
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{ 0xf000, 0x9000, thumb_disasm_ldrsprel },
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{ 0xf000, 0x9000, thumb_disasm_ldrsprel },
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{ 0xff00, 0xb000, thumb_disasm_addsprel },
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{ 0xe000, 0x6000, thumb_disasm_ldrimm },
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{ 0xe000, 0x6000, thumb_disasm_ldrimm },
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{ 0xe000, 0x2000, thumb_disasm_immop },
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{ 0xe000, 0x2000, thumb_disasm_immop },
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{ 0xf000, 0xd000, thumb_disasm_condbranch },
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{ 0xff00, 0xdf00, thumb_disasm_swi },
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{ 0xff00, 0xdf00, thumb_disasm_swi },
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{ 0xff00, 0xbf00, thumb_disasm_nop },
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{ 0xff00, 0xbf00, thumb_disasm_nop },
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{ 0xfc00, 0x1c00, thumb_disasm_addsub },
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{ 0xe000, 0x0000, thumb_disasm_movshift },
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{ 0x0000, 0x0000, NULL }
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{ 0x0000, 0x0000, NULL }
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};
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};
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