345 lines
14 KiB
C
345 lines
14 KiB
C
/* Definitions for opcode table for the sparc.
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Copyright (C) 1989-2019 Free Software Foundation, Inc.
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This file is part of GAS, the GNU Assembler, GDB, the GNU debugger, and
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the GNU Binutils.
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GAS/GDB is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3, or (at your option)
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any later version.
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GAS/GDB is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with GAS or GDB; see the file COPYING3. If not, write to
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the Free Software Foundation, 51 Franklin Street - Fifth Floor,
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Boston, MA 02110-1301, USA. */
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#include "ansidecl.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* The SPARC opcode table (and other related data) is defined in
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the opcodes library in sparc-opc.c. If you change anything here, make
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sure you fix up that file, and vice versa. */
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/* FIXME-someday: perhaps the ,a's and such should be embedded in the
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instruction's name rather than the args. This would make gas faster, pinsn
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slower, but would mess up some macros a bit. xoxorich. */
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/* List of instruction sets variations.
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These values are such that each element is either a superset of a
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preceding each one or they conflict in which case SPARC_OPCODE_CONFLICT_P
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returns non-zero.
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The values are indices into `sparc_opcode_archs' defined in sparc-opc.c.
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Don't change this without updating sparc-opc.c. */
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enum sparc_opcode_arch_val
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{
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SPARC_OPCODE_ARCH_V6 = 0,
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SPARC_OPCODE_ARCH_V7,
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SPARC_OPCODE_ARCH_V8,
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SPARC_OPCODE_ARCH_LEON,
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SPARC_OPCODE_ARCH_SPARCLET,
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SPARC_OPCODE_ARCH_SPARCLITE,
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/* V9 variants must appear last. */
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SPARC_OPCODE_ARCH_V9,
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SPARC_OPCODE_ARCH_V9A, /* V9 with ultrasparc additions. */
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SPARC_OPCODE_ARCH_V9B, /* V9 with ultrasparc and cheetah additions. */
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SPARC_OPCODE_ARCH_V9C, /* V9 with UA2005 and T1 additions. */
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SPARC_OPCODE_ARCH_V9D, /* V9 with UA2007 and T3 additions. */
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SPARC_OPCODE_ARCH_V9E, /* V9 with OSA2011 and T4 additions modulus integer multiply-add. */
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SPARC_OPCODE_ARCH_V9V, /* V9 with OSA2011 and T4 additions, integer
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multiply and Fujitsu fp multiply-add. */
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SPARC_OPCODE_ARCH_V9M, /* V9 with OSA2015 and M7 additions. */
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SPARC_OPCODE_ARCH_M8, /* V9 with OSA2017 and M8 additions. */
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SPARC_OPCODE_ARCH_MAX = SPARC_OPCODE_ARCH_M8,
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SPARC_OPCODE_ARCH_BAD /* Error return from sparc_opcode_lookup_arch. */
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};
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/* Given an enum sparc_opcode_arch_val, return the bitmask to use in
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insn encoding/decoding. */
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#define SPARC_OPCODE_ARCH_MASK(arch) (1 << (arch))
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/* Given a valid sparc_opcode_arch_val, return non-zero if it's v9. */
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#define SPARC_OPCODE_ARCH_V9_P(arch) ((arch) >= SPARC_OPCODE_ARCH_V9)
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/* Table of cpu variants. */
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typedef struct sparc_opcode_arch
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{
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const char *name;
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/* Mask of sparc_opcode_arch_val's supported.
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EG: For v7 this would be
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(SPARC_OPCODE_ARCH_MASK (..._V6) | SPARC_OPCODE_ARCH_MASK (..._V7)).
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These are short's because sparc_opcode.architecture is. */
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short supported;
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/* Bitmaps describing the set of hardware capabilities implemented
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by the opcode arch. */
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int hwcaps;
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int hwcaps2;
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} sparc_opcode_arch;
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extern const struct sparc_opcode_arch sparc_opcode_archs[];
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/* Given architecture name, look up it's sparc_opcode_arch_val value. */
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extern enum sparc_opcode_arch_val sparc_opcode_lookup_arch (const char *);
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/* Return the bitmask of supported architectures for ARCH. */
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#define SPARC_OPCODE_SUPPORTED(ARCH) (sparc_opcode_archs[ARCH].supported)
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/* Non-zero if ARCH1 conflicts with ARCH2.
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IE: ARCH1 as a supported bit set that ARCH2 doesn't, and vice versa. */
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#define SPARC_OPCODE_CONFLICT_P(ARCH1, ARCH2) \
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(((SPARC_OPCODE_SUPPORTED (ARCH1) & SPARC_OPCODE_SUPPORTED (ARCH2)) \
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!= SPARC_OPCODE_SUPPORTED (ARCH1)) \
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&& ((SPARC_OPCODE_SUPPORTED (ARCH1) & SPARC_OPCODE_SUPPORTED (ARCH2)) \
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!= SPARC_OPCODE_SUPPORTED (ARCH2)))
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/* Structure of an opcode table entry. */
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typedef struct sparc_opcode
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{
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const char *name;
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unsigned long match; /* Bits that must be set. */
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unsigned long lose; /* Bits that must not be set. */
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const char *args;
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/* This was called "delayed" in versions before the flags. */
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unsigned int flags;
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unsigned int hwcaps;
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unsigned int hwcaps2;
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short architecture; /* Bitmask of sparc_opcode_arch_val's. */
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} sparc_opcode;
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/* Struct for ASIs - to handle ASIs introduced in a specific architecture */
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typedef struct
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{
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int value;
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const char *name;
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short architecture;
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} sparc_asi;
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/* FIXME: Add F_ANACHRONISTIC flag for v9. */
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#define F_DELAYED 0x00000001 /* Delayed branch. */
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#define F_ALIAS 0x00000002 /* Alias for a "real" instruction. */
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#define F_UNBR 0x00000004 /* Unconditional branch. */
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#define F_CONDBR 0x00000008 /* Conditional branch. */
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#define F_JSR 0x00000010 /* Subroutine call. */
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#define F_FLOAT 0x00000020 /* Floating point instruction (not a branch). */
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#define F_FBR 0x00000040 /* Floating point branch. */
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#define F_PREFERRED 0x00000080 /* A preferred alias. */
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#define F_PREF_ALIAS (F_ALIAS|F_PREFERRED)
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/* These must match the ELF_SPARC_HWCAP_* and ELF_SPARC_HWCAP2_*
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values precisely. See include/elf/sparc.h. */
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#define HWCAP_MUL32 0x00000001 /* umul/umulcc/smul/smulcc insns */
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#define HWCAP_DIV32 0x00000002 /* udiv/udivcc/sdiv/sdivcc insns */
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#define HWCAP_FSMULD 0x00000004 /* 'fsmuld' insn */
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#define HWCAP_V8PLUS 0x00000008 /* v9 insns available to 32bit */
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#define HWCAP_POPC 0x00000010 /* 'popc' insn */
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#define HWCAP_VIS 0x00000020 /* VIS insns */
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#define HWCAP_VIS2 0x00000040 /* VIS2 insns */
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#define HWCAP_ASI_BLK_INIT \
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0x00000080 /* block init ASIs */
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#define HWCAP_FMAF 0x00000100 /* fused multiply-add */
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#define HWCAP_VIS3 0x00000400 /* VIS3 insns */
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#define HWCAP_HPC 0x00000800 /* HPC insns */
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#define HWCAP_RANDOM 0x00001000 /* 'random' insn */
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#define HWCAP_TRANS 0x00002000 /* transaction insns */
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#define HWCAP_FJFMAU 0x00004000 /* unfused multiply-add */
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#define HWCAP_IMA 0x00008000 /* integer multiply-add */
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#define HWCAP_ASI_CACHE_SPARING \
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0x00010000 /* cache sparing ASIs */
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#define HWCAP_AES 0x00020000 /* AES crypto insns */
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#define HWCAP_DES 0x00040000 /* DES crypto insns */
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#define HWCAP_KASUMI 0x00080000 /* KASUMI crypto insns */
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#define HWCAP_CAMELLIA 0x00100000 /* CAMELLIA crypto insns */
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#define HWCAP_MD5 0x00200000 /* MD5 hashing insns */
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#define HWCAP_SHA1 0x00400000 /* SHA1 hashing insns */
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#define HWCAP_SHA256 0x00800000 /* SHA256 hashing insns */
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#define HWCAP_SHA512 0x01000000 /* SHA512 hashing insns */
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#define HWCAP_MPMUL 0x02000000 /* Multiple Precision Multiply */
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#define HWCAP_MONT 0x04000000 /* Montgomery Mult/Sqrt */
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#define HWCAP_PAUSE 0x08000000 /* Pause insn */
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#define HWCAP_CBCOND 0x10000000 /* Compare and Branch insns */
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#define HWCAP_CRC32C 0x20000000 /* CRC32C insn */
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#define HWCAP2_FJATHPLUS 0x00000001 /* Fujitsu Athena+ */
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#define HWCAP2_VIS3B 0x00000002 /* Subset of VIS3 present on sparc64 X+. */
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#define HWCAP2_ADP 0x00000004 /* Application Data Protection */
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#define HWCAP2_SPARC5 0x00000008 /* The 29 new fp and sub instructions */
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#define HWCAP2_MWAIT 0x00000010 /* mwait instruction and load/monitor ASIs */
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#define HWCAP2_XMPMUL 0x00000020 /* XOR multiple precision multiply */
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#define HWCAP2_XMONT 0x00000040 /* XOR Montgomery mult/sqr instructions */
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#define HWCAP2_NSEC \
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0x00000080 /* pause insn with support for nsec timings */
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#define HWCAP2_FJATHHPC 0x00001000 /* Fujitsu HPC instrs */
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#define HWCAP2_FJDES 0x00002000 /* Fujitsu DES instrs */
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#define HWCAP2_FJAES 0x00010000 /* Fujitsu AES instrs */
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#define HWCAP2_SPARC6 0x00020000 /* OSA2017 new instructions */
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#define HWCAP2_ONADDSUB 0x00040000 /* Oracle Number add/subtract */
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#define HWCAP2_ONMUL 0x00080000 /* Oracle Number multiply */
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#define HWCAP2_ONDIV 0x00100000 /* Oracle Number divide */
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#define HWCAP2_DICTUNP 0x00200000 /* Dictionary unpack instruction */
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#define HWCAP2_FPCMPSHL 0x00400000 /* Partition compare with shifted result */
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#define HWCAP2_RLE 0x00800000 /* Run-length encoded burst and length */
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#define HWCAP2_SHA3 0x01000000 /* SHA3 instruction */
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/* All sparc opcodes are 32 bits, except for the `set' instruction (really a
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macro), which is 64 bits. It is handled as a special case.
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The match component is a mask saying which bits must match a particular
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opcode in order for an instruction to be an instance of that opcode.
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The args component is a string containing one character for each operand of the
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instruction.
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Kinds of operands:
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# Number used by optimizer. It is ignored.
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1 rs1 register.
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2 rs2 register.
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d rd register.
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e frs1 floating point register.
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v frs1 floating point register (double/even).
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V frs1 floating point register (quad/multiple of 4).
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; frs1 floating piont register (multiple of 8).
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f frs2 floating point register.
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B frs2 floating point register (double/even).
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R frs2 floating point register (quad/multiple of 4).
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: frs2 floating point register (multiple of 8).
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' rs2m floating point register (double/even) in FPCMPSHL. (m8)
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4 frs3 floating point register.
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5 frs3 floating point register (doube/even).
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g frsd floating point register.
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H frsd floating point register (double/even).
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J frsd floating point register (quad/multiple of 4).
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} frsd floating point register (double/even) that is == frs2
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^ frsd floating piont register in ON instructions.
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b crs1 coprocessor register
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c crs2 coprocessor register
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D crsd coprocessor register
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m alternate space register (asr) in rd
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M alternate space register (asr) in rs1
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h 22 high bits.
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X 5 bit unsigned immediate
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Y 6 bit unsigned immediate
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3 SIAM mode (3 bits). (v9b)
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K MEMBAR mask (7 bits). (v9)
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j 10 bit Immediate. (v9)
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I 11 bit Immediate. (v9)
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i 13 bit Immediate.
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n 22 bit immediate.
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k 2+14 bit PC relative immediate. (v9)
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G 19 bit PC relative immediate. (v9)
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l 22 bit PC relative immediate.
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L 30 bit PC relative immediate.
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a Annul. The annul bit is set.
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A Alternate address space. Stored as 8 bits.
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C Coprocessor state register.
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F floating point state register.
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p Processor state register.
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N Branch predict clear ",pn" (v9)
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T Branch predict set ",pt" (v9)
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z %icc. (v9)
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Z %xcc. (v9)
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q Floating point queue.
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r Single register that is both rs1 and rd.
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O Single register that is both rs2 and rd.
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Q Coprocessor queue.
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S Special case.
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t Trap base register.
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w Window invalid mask register.
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y Y register.
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u sparclet coprocessor registers in rd position
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U sparclet coprocessor registers in rs1 position
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E %ccr. (v9)
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s %fprs. (v9)
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P %pc. (v9)
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W %tick. (v9)
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{ %mcdper. (v9b)
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& %entropy. (m8)
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o %asi. (v9)
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6 %fcc0. (v9)
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7 %fcc1. (v9)
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8 %fcc2. (v9)
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9 %fcc3. (v9)
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! Privileged Register in rd (v9)
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? Privileged Register in rs1 (v9)
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% Hyperprivileged Register in rd (v9b)
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$ Hyperprivileged Register in rs1 (v9b)
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* Prefetch function constant. (v9)
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x OPF field (v9 impdep).
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0 32/64 bit immediate for set or setx (v9) insns
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_ Ancillary state register in rd (v9a)
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/ Ancillary state register in rs1 (v9a)
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( entire floating point state register (%efsr)
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) 5 bit immediate placed in RS3 field
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= 2+8 bit PC relative immediate. (v9)
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| FPCMPSHL 2 bit immediate. (m8) */
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#define OP2(x) (((x) & 0x7) << 22) /* Op2 field of format2 insns. */
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#define OP3(x) (((x) & 0x3f) << 19) /* Op3 field of format3 insns. */
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#define OP(x) ((unsigned) ((x) & 0x3) << 30) /* Op field of all insns. */
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#define OPF(x) (((x) & 0x1ff) << 5) /* Opf field of float insns. */
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#define OPF_LOW5(x) OPF ((x) & 0x1f) /* V9. */
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#define OPF_LOW4(x) OPF ((x) & 0xf) /* V9. */
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#define OPM(x) (((x) & 0x7) << 10) /* opm field of misaligned load/store insns. */
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#define OPMI(x) (((x) & 0x1) << 9) /* opm i field of misaligned load/store insns. */
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#define ONFCN(x) (((x) & 0x3) << 26) /* fcn field of Oracle Number insns. */
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#define REVFCN(x) (((x) & 0x3) << 0) /* fcn field of REV* insns. */
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#define F3F(x, y, z) (OP (x) | OP3 (y) | OPF (z)) /* Format3 float insns. */
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#define F3F4(x, y, z) (OP (x) | OP3 (y) | OPF_LOW4 (z))
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#define F3I(x) (((x) & 0x1) << 13) /* Immediate field of format 3 insns. */
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#define F2(x, y) (OP (x) | OP2(y)) /* Format 2 insns. */
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#define F3(x, y, z) (OP (x) | OP3(y) | F3I(z)) /* Format3 insns. */
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#define F1(x) (OP (x))
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#define DISP30(x) ((x) & 0x3fffffff)
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#define ASI(x) (((x) & 0xff) << 5) /* Asi field of format3 insns. */
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#define RS2(x) ((x) & 0x1f) /* Rs2 field. */
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#define SIMM13(x) ((x) & 0x1fff) /* Simm13 field. */
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#define SIMM10(x) ((x) & 0x3ff) /* Simm10 field. */
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#define RD(x) (((x) & 0x1f) << 25) /* Destination register field. */
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#define RS1(x) (((x) & 0x1f) << 14) /* Rs1 field. */
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#define RS3(x) (((x) & 0x1f) << 9) /* Rs3 field. */
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#define ASI_RS2(x) (SIMM13 (x))
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#define MEMBAR(x) ((x) & 0x7f)
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#define SLCPOP(x) (((x) & 0x7f) << 6) /* Sparclet cpop. */
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#define ANNUL (1 << 29)
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#define BPRED (1 << 19) /* V9. */
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#define IMMED F3I (1)
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#define RD_G0 RD (~0)
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#define RS1_G0 RS1 (~0)
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#define RS2_G0 RS2 (~0)
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extern const struct sparc_opcode sparc_opcodes[];
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extern const int sparc_num_opcodes;
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extern const sparc_asi *sparc_encode_asi (const char *);
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extern const char *sparc_decode_asi (int);
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extern int sparc_encode_membar (const char *);
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extern const char *sparc_decode_membar (int);
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extern int sparc_encode_prefetch (const char *);
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extern const char *sparc_decode_prefetch (int);
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extern int sparc_encode_sparclet_cpreg (const char *);
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extern const char *sparc_decode_sparclet_cpreg (int);
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/* Local Variables:
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fill-column: 131
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comment-column: 0
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End: */
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#ifdef __cplusplus
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}
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#endif
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