558 lines
15 KiB
C
558 lines
15 KiB
C
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/* RISC-V disassembler
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Copyright (C) 2011-2019 Free Software Foundation, Inc.
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Contributed by Andrew Waterman (andrew@sifive.com).
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Based on MIPS target.
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This file is part of the GNU opcodes library.
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This library is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3, or (at your option)
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any later version.
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It is distributed in the hope that it will be useful, but WITHOUT
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; see the file COPYING3. If not,
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see <http://www.gnu.org/licenses/>. */
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#include "sysdep.h"
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#include "disassemble.h"
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#include "libiberty.h"
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#include "opcode/riscv.h"
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#include "opintl.h"
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#include "elf-bfd.h"
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#include "elf/riscv.h"
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#include "bfd_stdint.h"
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#include <ctype.h>
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struct riscv_private_data
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{
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bfd_vma gp;
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bfd_vma print_addr;
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bfd_vma hi_addr[OP_MASK_RD + 1];
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};
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static const char * const *riscv_gpr_names;
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static const char * const *riscv_fpr_names;
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/* Other options. */
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static int no_aliases; /* If set disassemble as most general inst. */
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static void
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set_default_riscv_dis_options (void)
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{
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riscv_gpr_names = riscv_gpr_names_abi;
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riscv_fpr_names = riscv_fpr_names_abi;
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no_aliases = 0;
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}
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static void
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parse_riscv_dis_option (const char *option)
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{
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if (strcmp (option, "no-aliases") == 0)
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no_aliases = 1;
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else if (strcmp (option, "numeric") == 0)
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{
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riscv_gpr_names = riscv_gpr_names_numeric;
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riscv_fpr_names = riscv_fpr_names_numeric;
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}
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else
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{
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/* xgettext:c-format */
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opcodes_error_handler (_("unrecognized disassembler option: %s"), option);
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}
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}
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static void
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parse_riscv_dis_options (const char *opts_in)
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{
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char *opts = xstrdup (opts_in), *opt = opts, *opt_end = opts;
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set_default_riscv_dis_options ();
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for ( ; opt_end != NULL; opt = opt_end + 1)
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{
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if ((opt_end = strchr (opt, ',')) != NULL)
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*opt_end = 0;
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parse_riscv_dis_option (opt);
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}
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free (opts);
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}
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/* Print one argument from an array. */
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static void
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arg_print (struct disassemble_info *info, unsigned long val,
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const char* const* array, size_t size)
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{
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const char *s = val >= size || array[val] == NULL ? "unknown" : array[val];
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(*info->fprintf_func) (info->stream, "%s", s);
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}
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static void
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maybe_print_address (struct riscv_private_data *pd, int base_reg, int offset)
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{
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if (pd->hi_addr[base_reg] != (bfd_vma)-1)
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{
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pd->print_addr = (base_reg != 0 ? pd->hi_addr[base_reg] : 0) + offset;
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pd->hi_addr[base_reg] = -1;
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}
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else if (base_reg == X_GP && pd->gp != (bfd_vma)-1)
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pd->print_addr = pd->gp + offset;
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else if (base_reg == X_TP || base_reg == 0)
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pd->print_addr = offset;
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}
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/* Print insn arguments for 32/64-bit code. */
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static void
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print_insn_args (const char *d, insn_t l, bfd_vma pc, disassemble_info *info)
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{
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struct riscv_private_data *pd = info->private_data;
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int rs1 = (l >> OP_SH_RS1) & OP_MASK_RS1;
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int rd = (l >> OP_SH_RD) & OP_MASK_RD;
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fprintf_ftype print = info->fprintf_func;
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if (*d != '\0')
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print (info->stream, "\t");
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for (; *d != '\0'; d++)
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{
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switch (*d)
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{
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case 'C': /* RVC */
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switch (*++d)
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{
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case 's': /* RS1 x8-x15 */
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case 'w': /* RS1 x8-x15 */
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print (info->stream, "%s",
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riscv_gpr_names[EXTRACT_OPERAND (CRS1S, l) + 8]);
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break;
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case 't': /* RS2 x8-x15 */
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case 'x': /* RS2 x8-x15 */
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print (info->stream, "%s",
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riscv_gpr_names[EXTRACT_OPERAND (CRS2S, l) + 8]);
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break;
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case 'U': /* RS1, constrained to equal RD */
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print (info->stream, "%s", riscv_gpr_names[rd]);
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break;
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case 'c': /* RS1, constrained to equal sp */
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print (info->stream, "%s", riscv_gpr_names[X_SP]);
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break;
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case 'V': /* RS2 */
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print (info->stream, "%s",
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riscv_gpr_names[EXTRACT_OPERAND (CRS2, l)]);
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break;
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case 'i':
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print (info->stream, "%d", (int)EXTRACT_RVC_SIMM3 (l));
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break;
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case 'o':
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case 'j':
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print (info->stream, "%d", (int)EXTRACT_RVC_IMM (l));
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break;
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case 'k':
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print (info->stream, "%d", (int)EXTRACT_RVC_LW_IMM (l));
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break;
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case 'l':
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print (info->stream, "%d", (int)EXTRACT_RVC_LD_IMM (l));
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break;
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case 'm':
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print (info->stream, "%d", (int)EXTRACT_RVC_LWSP_IMM (l));
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break;
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case 'n':
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print (info->stream, "%d", (int)EXTRACT_RVC_LDSP_IMM (l));
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break;
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case 'K':
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print (info->stream, "%d", (int)EXTRACT_RVC_ADDI4SPN_IMM (l));
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break;
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case 'L':
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print (info->stream, "%d", (int)EXTRACT_RVC_ADDI16SP_IMM (l));
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break;
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case 'M':
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print (info->stream, "%d", (int)EXTRACT_RVC_SWSP_IMM (l));
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break;
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case 'N':
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print (info->stream, "%d", (int)EXTRACT_RVC_SDSP_IMM (l));
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break;
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case 'p':
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info->target = EXTRACT_RVC_B_IMM (l) + pc;
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(*info->print_address_func) (info->target, info);
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break;
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case 'a':
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info->target = EXTRACT_RVC_J_IMM (l) + pc;
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(*info->print_address_func) (info->target, info);
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break;
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case 'u':
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print (info->stream, "0x%x",
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(int)(EXTRACT_RVC_IMM (l) & (RISCV_BIGIMM_REACH-1)));
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break;
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case '>':
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print (info->stream, "0x%x", (int)EXTRACT_RVC_IMM (l) & 0x3f);
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break;
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case '<':
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print (info->stream, "0x%x", (int)EXTRACT_RVC_IMM (l) & 0x1f);
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break;
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case 'T': /* floating-point RS2 */
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print (info->stream, "%s",
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riscv_fpr_names[EXTRACT_OPERAND (CRS2, l)]);
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break;
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case 'D': /* floating-point RS2 x8-x15 */
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print (info->stream, "%s",
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riscv_fpr_names[EXTRACT_OPERAND (CRS2S, l) + 8]);
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break;
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}
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break;
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case ',':
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case '(':
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case ')':
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case '[':
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case ']':
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print (info->stream, "%c", *d);
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break;
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case '0':
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/* Only print constant 0 if it is the last argument */
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if (!d[1])
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print (info->stream, "0");
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break;
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case 'b':
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case 's':
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if ((l & MASK_JALR) == MATCH_JALR)
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maybe_print_address (pd, rs1, 0);
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print (info->stream, "%s", riscv_gpr_names[rs1]);
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break;
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case 't':
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print (info->stream, "%s",
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riscv_gpr_names[EXTRACT_OPERAND (RS2, l)]);
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break;
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case 'u':
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print (info->stream, "0x%x",
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(unsigned)EXTRACT_UTYPE_IMM (l) >> RISCV_IMM_BITS);
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break;
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case 'm':
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arg_print (info, EXTRACT_OPERAND (RM, l),
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riscv_rm, ARRAY_SIZE (riscv_rm));
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break;
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case 'P':
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arg_print (info, EXTRACT_OPERAND (PRED, l),
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riscv_pred_succ, ARRAY_SIZE (riscv_pred_succ));
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break;
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case 'Q':
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arg_print (info, EXTRACT_OPERAND (SUCC, l),
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riscv_pred_succ, ARRAY_SIZE (riscv_pred_succ));
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break;
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case 'o':
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maybe_print_address (pd, rs1, EXTRACT_ITYPE_IMM (l));
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/* Fall through. */
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case 'j':
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if (((l & MASK_ADDI) == MATCH_ADDI && rs1 != 0)
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|| (l & MASK_JALR) == MATCH_JALR)
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maybe_print_address (pd, rs1, EXTRACT_ITYPE_IMM (l));
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print (info->stream, "%d", (int)EXTRACT_ITYPE_IMM (l));
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break;
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case 'q':
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maybe_print_address (pd, rs1, EXTRACT_STYPE_IMM (l));
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print (info->stream, "%d", (int)EXTRACT_STYPE_IMM (l));
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break;
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case 'a':
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info->target = EXTRACT_UJTYPE_IMM (l) + pc;
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(*info->print_address_func) (info->target, info);
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break;
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case 'p':
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info->target = EXTRACT_SBTYPE_IMM (l) + pc;
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(*info->print_address_func) (info->target, info);
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break;
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case 'd':
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if ((l & MASK_AUIPC) == MATCH_AUIPC)
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pd->hi_addr[rd] = pc + EXTRACT_UTYPE_IMM (l);
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else if ((l & MASK_LUI) == MATCH_LUI)
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pd->hi_addr[rd] = EXTRACT_UTYPE_IMM (l);
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else if ((l & MASK_C_LUI) == MATCH_C_LUI)
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pd->hi_addr[rd] = EXTRACT_RVC_LUI_IMM (l);
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print (info->stream, "%s", riscv_gpr_names[rd]);
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break;
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case 'z':
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print (info->stream, "%s", riscv_gpr_names[0]);
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break;
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case '>':
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print (info->stream, "0x%x", (int)EXTRACT_OPERAND (SHAMT, l));
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break;
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case '<':
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print (info->stream, "0x%x", (int)EXTRACT_OPERAND (SHAMTW, l));
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break;
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case 'S':
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case 'U':
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print (info->stream, "%s", riscv_fpr_names[rs1]);
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break;
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case 'T':
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print (info->stream, "%s", riscv_fpr_names[EXTRACT_OPERAND (RS2, l)]);
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break;
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case 'D':
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print (info->stream, "%s", riscv_fpr_names[rd]);
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break;
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case 'R':
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print (info->stream, "%s", riscv_fpr_names[EXTRACT_OPERAND (RS3, l)]);
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break;
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case 'E':
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{
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const char* csr_name = NULL;
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unsigned int csr = EXTRACT_OPERAND (CSR, l);
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switch (csr)
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{
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#define DECLARE_CSR(name, num) case num: csr_name = #name; break;
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#include "opcode/riscv-opc.h"
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#undef DECLARE_CSR
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}
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if (csr_name)
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print (info->stream, "%s", csr_name);
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else
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print (info->stream, "0x%x", csr);
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break;
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}
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case 'Z':
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print (info->stream, "%d", rs1);
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break;
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default:
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/* xgettext:c-format */
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print (info->stream, _("# internal error, undefined modifier (%c)"),
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*d);
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return;
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}
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}
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}
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/* Print the RISC-V instruction at address MEMADDR in debugged memory,
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on using INFO. Returns length of the instruction, in bytes.
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BIGENDIAN must be 1 if this is big-endian code, 0 if
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this is little-endian code. */
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static int
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riscv_disassemble_insn (bfd_vma memaddr, insn_t word, disassemble_info *info)
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{
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|
|
const struct riscv_opcode *op;
|
||
|
|
static bfd_boolean init = 0;
|
||
|
|
static const struct riscv_opcode *riscv_hash[OP_MASK_OP + 1];
|
||
|
|
struct riscv_private_data *pd;
|
||
|
|
int insnlen;
|
||
|
|
|
||
|
|
#define OP_HASH_IDX(i) ((i) & (riscv_insn_length (i) == 2 ? 0x3 : OP_MASK_OP))
|
||
|
|
|
||
|
|
/* Build a hash table to shorten the search time. */
|
||
|
|
if (! init)
|
||
|
|
{
|
||
|
|
for (op = riscv_opcodes; op->name; op++)
|
||
|
|
if (!riscv_hash[OP_HASH_IDX (op->match)])
|
||
|
|
riscv_hash[OP_HASH_IDX (op->match)] = op;
|
||
|
|
|
||
|
|
init = 1;
|
||
|
|
}
|
||
|
|
|
||
|
|
if (info->private_data == NULL)
|
||
|
|
{
|
||
|
|
int i;
|
||
|
|
|
||
|
|
pd = info->private_data = xcalloc (1, sizeof (struct riscv_private_data));
|
||
|
|
pd->gp = -1;
|
||
|
|
pd->print_addr = -1;
|
||
|
|
for (i = 0; i < (int)ARRAY_SIZE (pd->hi_addr); i++)
|
||
|
|
pd->hi_addr[i] = -1;
|
||
|
|
|
||
|
|
for (i = 0; i < info->symtab_size; i++)
|
||
|
|
if (strcmp (bfd_asymbol_name (info->symtab[i]), RISCV_GP_SYMBOL) == 0)
|
||
|
|
pd->gp = bfd_asymbol_value (info->symtab[i]);
|
||
|
|
}
|
||
|
|
else
|
||
|
|
pd = info->private_data;
|
||
|
|
|
||
|
|
insnlen = riscv_insn_length (word);
|
||
|
|
|
||
|
|
/* RISC-V instructions are always little-endian. */
|
||
|
|
info->endian_code = BFD_ENDIAN_LITTLE;
|
||
|
|
|
||
|
|
info->bytes_per_chunk = insnlen % 4 == 0 ? 4 : 2;
|
||
|
|
info->bytes_per_line = 8;
|
||
|
|
/* We don't support constant pools, so this must be code. */
|
||
|
|
info->display_endian = info->endian_code;
|
||
|
|
info->insn_info_valid = 1;
|
||
|
|
info->branch_delay_insns = 0;
|
||
|
|
info->data_size = 0;
|
||
|
|
info->insn_type = dis_nonbranch;
|
||
|
|
info->target = 0;
|
||
|
|
info->target2 = 0;
|
||
|
|
|
||
|
|
op = riscv_hash[OP_HASH_IDX (word)];
|
||
|
|
if (op != NULL)
|
||
|
|
{
|
||
|
|
unsigned xlen = 0;
|
||
|
|
|
||
|
|
/* If XLEN is not known, get its value from the ELF class. */
|
||
|
|
if (info->mach == bfd_mach_riscv64)
|
||
|
|
xlen = 64;
|
||
|
|
else if (info->mach == bfd_mach_riscv32)
|
||
|
|
xlen = 32;
|
||
|
|
else if (info->section != NULL)
|
||
|
|
{
|
||
|
|
Elf_Internal_Ehdr *ehdr = elf_elfheader (info->section->owner);
|
||
|
|
xlen = ehdr->e_ident[EI_CLASS] == ELFCLASS64 ? 64 : 32;
|
||
|
|
}
|
||
|
|
|
||
|
|
for (; op->name; op++)
|
||
|
|
{
|
||
|
|
/* Does the opcode match? */
|
||
|
|
if (! (op->match_func) (op, word))
|
||
|
|
continue;
|
||
|
|
/* Is this a pseudo-instruction and may we print it as such? */
|
||
|
|
if (no_aliases && (op->pinfo & INSN_ALIAS))
|
||
|
|
continue;
|
||
|
|
/* Is this instruction restricted to a certain value of XLEN? */
|
||
|
|
if ((op->xlen_requirement != 0) && (op->xlen_requirement != xlen))
|
||
|
|
continue;
|
||
|
|
|
||
|
|
/* It's a match. */
|
||
|
|
(*info->fprintf_func) (info->stream, "%s", op->name);
|
||
|
|
print_insn_args (op->args, word, memaddr, info);
|
||
|
|
|
||
|
|
/* Try to disassemble multi-instruction addressing sequences. */
|
||
|
|
if (pd->print_addr != (bfd_vma)-1)
|
||
|
|
{
|
||
|
|
info->target = pd->print_addr;
|
||
|
|
(*info->fprintf_func) (info->stream, " # ");
|
||
|
|
(*info->print_address_func) (info->target, info);
|
||
|
|
pd->print_addr = -1;
|
||
|
|
}
|
||
|
|
|
||
|
|
/* Finish filling out insn_info fields. */
|
||
|
|
switch (op->pinfo & INSN_TYPE)
|
||
|
|
{
|
||
|
|
case INSN_BRANCH:
|
||
|
|
info->insn_type = dis_branch;
|
||
|
|
break;
|
||
|
|
case INSN_CONDBRANCH:
|
||
|
|
info->insn_type = dis_condbranch;
|
||
|
|
break;
|
||
|
|
case INSN_JSR:
|
||
|
|
info->insn_type = dis_jsr;
|
||
|
|
break;
|
||
|
|
case INSN_DREF:
|
||
|
|
info->insn_type = dis_dref;
|
||
|
|
break;
|
||
|
|
default:
|
||
|
|
break;
|
||
|
|
}
|
||
|
|
|
||
|
|
if (op->pinfo & INSN_DATA_SIZE)
|
||
|
|
{
|
||
|
|
int size = ((op->pinfo & INSN_DATA_SIZE)
|
||
|
|
>> INSN_DATA_SIZE_SHIFT);
|
||
|
|
info->data_size = 1 << (size - 1);
|
||
|
|
}
|
||
|
|
|
||
|
|
return insnlen;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
/* We did not find a match, so just print the instruction bits. */
|
||
|
|
info->insn_type = dis_noninsn;
|
||
|
|
(*info->fprintf_func) (info->stream, "0x%llx", (unsigned long long)word);
|
||
|
|
return insnlen;
|
||
|
|
}
|
||
|
|
|
||
|
|
int
|
||
|
|
print_insn_riscv (bfd_vma memaddr, struct disassemble_info *info)
|
||
|
|
{
|
||
|
|
bfd_byte packet[2];
|
||
|
|
insn_t insn = 0;
|
||
|
|
bfd_vma n;
|
||
|
|
int status;
|
||
|
|
|
||
|
|
if (info->disassembler_options != NULL)
|
||
|
|
{
|
||
|
|
parse_riscv_dis_options (info->disassembler_options);
|
||
|
|
/* Avoid repeatedly parsing the options. */
|
||
|
|
info->disassembler_options = NULL;
|
||
|
|
}
|
||
|
|
else if (riscv_gpr_names == NULL)
|
||
|
|
set_default_riscv_dis_options ();
|
||
|
|
|
||
|
|
/* Instructions are a sequence of 2-byte packets in little-endian order. */
|
||
|
|
for (n = 0; n < sizeof (insn) && n < riscv_insn_length (insn); n += 2)
|
||
|
|
{
|
||
|
|
status = (*info->read_memory_func) (memaddr + n, packet, 2, info);
|
||
|
|
if (status != 0)
|
||
|
|
{
|
||
|
|
/* Don't fail just because we fell off the end. */
|
||
|
|
if (n > 0)
|
||
|
|
break;
|
||
|
|
(*info->memory_error_func) (status, memaddr, info);
|
||
|
|
return status;
|
||
|
|
}
|
||
|
|
|
||
|
|
insn |= ((insn_t) bfd_getl16 (packet)) << (8 * n);
|
||
|
|
}
|
||
|
|
|
||
|
|
return riscv_disassemble_insn (memaddr, insn, info);
|
||
|
|
}
|
||
|
|
|
||
|
|
/* Prevent use of the fake labels that are generated as part of the DWARF
|
||
|
|
and for relaxable relocations in the assembler. */
|
||
|
|
|
||
|
|
bfd_boolean
|
||
|
|
riscv_symbol_is_valid (asymbol * sym,
|
||
|
|
struct disassemble_info * info ATTRIBUTE_UNUSED)
|
||
|
|
{
|
||
|
|
const char * name;
|
||
|
|
|
||
|
|
if (sym == NULL)
|
||
|
|
return FALSE;
|
||
|
|
|
||
|
|
name = bfd_asymbol_name (sym);
|
||
|
|
|
||
|
|
return (strcmp (name, RISCV_FAKE_LABEL_NAME) != 0);
|
||
|
|
}
|
||
|
|
|
||
|
|
void
|
||
|
|
print_riscv_disassembler_options (FILE *stream)
|
||
|
|
{
|
||
|
|
fprintf (stream, _("\n\
|
||
|
|
The following RISC-V-specific disassembler options are supported for use\n\
|
||
|
|
with the -M switch (multiple options should be separated by commas):\n"));
|
||
|
|
|
||
|
|
fprintf (stream, _("\n\
|
||
|
|
numeric Print numeric register names, rather than ABI names.\n"));
|
||
|
|
|
||
|
|
fprintf (stream, _("\n\
|
||
|
|
no-aliases Disassemble only into canonical instructions, rather\n\
|
||
|
|
than into pseudoinstructions.\n"));
|
||
|
|
|
||
|
|
fprintf (stream, _("\n"));
|
||
|
|
}
|