mirror of https://github.com/odrling/Aegisub
294 lines
8.2 KiB
C
294 lines
8.2 KiB
C
/*
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** MIPS instruction emitter.
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** Copyright (C) 2005-2017 Mike Pall. See Copyright Notice in luajit.h
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*/
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#if LJ_64
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static intptr_t get_k64val(IRIns *ir)
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{
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if (ir->o == IR_KINT64) {
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return (intptr_t)ir_kint64(ir)->u64;
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} else if (ir->o == IR_KGC) {
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return (intptr_t)ir_kgc(ir);
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} else if (ir->o == IR_KPTR || ir->o == IR_KKPTR) {
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return (intptr_t)ir_kptr(ir);
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} else {
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lua_assert(ir->o == IR_KINT || ir->o == IR_KNULL);
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return ir->i; /* Sign-extended. */
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}
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}
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#endif
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#if LJ_64
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#define get_kval(ir) get_k64val(ir)
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#else
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#define get_kval(ir) ((ir)->i)
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#endif
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/* -- Emit basic instructions --------------------------------------------- */
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static void emit_dst(ASMState *as, MIPSIns mi, Reg rd, Reg rs, Reg rt)
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{
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*--as->mcp = mi | MIPSF_D(rd) | MIPSF_S(rs) | MIPSF_T(rt);
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}
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static void emit_dta(ASMState *as, MIPSIns mi, Reg rd, Reg rt, uint32_t a)
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{
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*--as->mcp = mi | MIPSF_D(rd) | MIPSF_T(rt) | MIPSF_A(a);
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}
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#define emit_ds(as, mi, rd, rs) emit_dst(as, (mi), (rd), (rs), 0)
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#define emit_tg(as, mi, rt, rg) emit_dst(as, (mi), (rg)&31, 0, (rt))
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static void emit_tsi(ASMState *as, MIPSIns mi, Reg rt, Reg rs, int32_t i)
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{
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*--as->mcp = mi | MIPSF_T(rt) | MIPSF_S(rs) | (i & 0xffff);
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}
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#define emit_ti(as, mi, rt, i) emit_tsi(as, (mi), (rt), 0, (i))
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#define emit_hsi(as, mi, rh, rs, i) emit_tsi(as, (mi), (rh) & 31, (rs), (i))
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static void emit_fgh(ASMState *as, MIPSIns mi, Reg rf, Reg rg, Reg rh)
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{
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*--as->mcp = mi | MIPSF_F(rf&31) | MIPSF_G(rg&31) | MIPSF_H(rh&31);
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}
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#define emit_fg(as, mi, rf, rg) emit_fgh(as, (mi), (rf), (rg), 0)
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static void emit_rotr(ASMState *as, Reg dest, Reg src, Reg tmp, uint32_t shift)
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{
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if (LJ_64 || (as->flags & JIT_F_MIPSXXR2)) {
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emit_dta(as, MIPSI_ROTR, dest, src, shift);
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} else {
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emit_dst(as, MIPSI_OR, dest, dest, tmp);
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emit_dta(as, MIPSI_SLL, dest, src, (-shift)&31);
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emit_dta(as, MIPSI_SRL, tmp, src, shift);
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}
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}
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#if LJ_64
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static void emit_tsml(ASMState *as, MIPSIns mi, Reg rt, Reg rs, uint32_t msb,
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uint32_t lsb)
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{
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*--as->mcp = mi | MIPSF_T(rt) | MIPSF_S(rs) | MIPSF_M(msb) | MIPSF_L(lsb);
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}
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#endif
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/* -- Emit loads/stores --------------------------------------------------- */
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/* Prefer rematerialization of BASE/L from global_State over spills. */
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#define emit_canremat(ref) ((ref) <= REF_BASE)
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/* Try to find a one step delta relative to another constant. */
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static int emit_kdelta1(ASMState *as, Reg t, intptr_t i)
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{
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RegSet work = ~as->freeset & RSET_GPR;
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while (work) {
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Reg r = rset_picktop(work);
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IRRef ref = regcost_ref(as->cost[r]);
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lua_assert(r != t);
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if (ref < ASMREF_L) {
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intptr_t delta = (intptr_t)((uintptr_t)i -
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(uintptr_t)(ra_iskref(ref) ? ra_krefk(as, ref) : get_kval(IR(ref))));
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if (checki16(delta)) {
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emit_tsi(as, MIPSI_AADDIU, t, r, delta);
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return 1;
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}
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}
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rset_clear(work, r);
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}
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return 0; /* Failed. */
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}
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/* Load a 32 bit constant into a GPR. */
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static void emit_loadi(ASMState *as, Reg r, int32_t i)
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{
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if (checki16(i)) {
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emit_ti(as, MIPSI_LI, r, i);
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} else {
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if ((i & 0xffff)) {
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intptr_t jgl = (intptr_t)(void *)J2G(as->J);
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if ((uintptr_t)(i-jgl) < 65536) {
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emit_tsi(as, MIPSI_ADDIU, r, RID_JGL, i-jgl-32768);
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return;
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} else if (emit_kdelta1(as, r, i)) {
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return;
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} else if ((i >> 16) == 0) {
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emit_tsi(as, MIPSI_ORI, r, RID_ZERO, i);
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return;
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}
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emit_tsi(as, MIPSI_ORI, r, r, i);
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}
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emit_ti(as, MIPSI_LUI, r, (i >> 16));
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}
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}
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#if LJ_64
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/* Load a 64 bit constant into a GPR. */
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static void emit_loadu64(ASMState *as, Reg r, uint64_t u64)
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{
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if (checki32((int64_t)u64)) {
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emit_loadi(as, r, (int32_t)u64);
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} else {
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uint64_t delta = u64 - (uint64_t)(void *)J2G(as->J);
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if (delta < 65536) {
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emit_tsi(as, MIPSI_DADDIU, r, RID_JGL, (int32_t)(delta-32768));
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} else if (emit_kdelta1(as, r, (intptr_t)u64)) {
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return;
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} else {
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if ((u64 & 0xffff)) {
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emit_tsi(as, MIPSI_ORI, r, r, u64 & 0xffff);
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}
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if (((u64 >> 16) & 0xffff)) {
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emit_dta(as, MIPSI_DSLL, r, r, 16);
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emit_tsi(as, MIPSI_ORI, r, r, (u64 >> 16) & 0xffff);
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emit_dta(as, MIPSI_DSLL, r, r, 16);
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} else {
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emit_dta(as, MIPSI_DSLL32, r, r, 0);
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}
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emit_loadi(as, r, (int32_t)(u64 >> 32));
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}
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/* TODO: There are probably more optimization opportunities. */
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}
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}
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#define emit_loada(as, r, addr) emit_loadu64(as, (r), u64ptr((addr)))
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#else
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#define emit_loada(as, r, addr) emit_loadi(as, (r), i32ptr((addr)))
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#endif
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static Reg ra_allock(ASMState *as, intptr_t k, RegSet allow);
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static void ra_allockreg(ASMState *as, intptr_t k, Reg r);
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/* Get/set from constant pointer. */
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static void emit_lsptr(ASMState *as, MIPSIns mi, Reg r, void *p, RegSet allow)
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{
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intptr_t jgl = (intptr_t)(J2G(as->J));
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intptr_t i = (intptr_t)(p);
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Reg base;
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if ((uint32_t)(i-jgl) < 65536) {
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i = i-jgl-32768;
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base = RID_JGL;
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} else {
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base = ra_allock(as, i-(int16_t)i, allow);
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}
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emit_tsi(as, mi, r, base, i);
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}
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#if LJ_64
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static void emit_loadk64(ASMState *as, Reg r, IRIns *ir)
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{
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const uint64_t *k = &ir_k64(ir)->u64;
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Reg r64 = r;
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if (rset_test(RSET_FPR, r)) {
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r64 = RID_TMP;
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emit_tg(as, MIPSI_DMTC1, r64, r);
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}
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if ((uint32_t)((intptr_t)k-(intptr_t)J2G(as->J)) < 65536)
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emit_lsptr(as, MIPSI_LD, r64, (void *)k, 0);
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else
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emit_loadu64(as, r64, *k);
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}
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#else
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#define emit_loadk64(as, r, ir) \
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emit_lsptr(as, MIPSI_LDC1, ((r) & 31), (void *)&ir_knum((ir))->u64, RSET_GPR)
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#endif
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/* Get/set global_State fields. */
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static void emit_lsglptr(ASMState *as, MIPSIns mi, Reg r, int32_t ofs)
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{
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emit_tsi(as, mi, r, RID_JGL, ofs-32768);
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}
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#define emit_getgl(as, r, field) \
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emit_lsglptr(as, MIPSI_AL, (r), (int32_t)offsetof(global_State, field))
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#define emit_setgl(as, r, field) \
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emit_lsglptr(as, MIPSI_AS, (r), (int32_t)offsetof(global_State, field))
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/* Trace number is determined from per-trace exit stubs. */
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#define emit_setvmstate(as, i) UNUSED(i)
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/* -- Emit control-flow instructions -------------------------------------- */
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/* Label for internal jumps. */
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typedef MCode *MCLabel;
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/* Return label pointing to current PC. */
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#define emit_label(as) ((as)->mcp)
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static void emit_branch(ASMState *as, MIPSIns mi, Reg rs, Reg rt, MCode *target)
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{
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MCode *p = as->mcp;
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ptrdiff_t delta = target - p;
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lua_assert(((delta + 0x8000) >> 16) == 0);
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*--p = mi | MIPSF_S(rs) | MIPSF_T(rt) | ((uint32_t)delta & 0xffffu);
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as->mcp = p;
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}
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static void emit_jmp(ASMState *as, MCode *target)
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{
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*--as->mcp = MIPSI_NOP;
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emit_branch(as, MIPSI_B, RID_ZERO, RID_ZERO, (target));
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}
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static void emit_call(ASMState *as, void *target, int needcfa)
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{
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MCode *p = as->mcp;
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*--p = MIPSI_NOP;
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if ((((uintptr_t)target ^ (uintptr_t)p) >> 28) == 0) {
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*--p = (((uintptr_t)target & 1) ? MIPSI_JALX : MIPSI_JAL) |
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(((uintptr_t)target >>2) & 0x03ffffffu);
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} else { /* Target out of range: need indirect call. */
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*--p = MIPSI_JALR | MIPSF_S(RID_CFUNCADDR);
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needcfa = 1;
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}
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as->mcp = p;
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if (needcfa) ra_allockreg(as, (intptr_t)target, RID_CFUNCADDR);
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}
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/* -- Emit generic operations --------------------------------------------- */
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#define emit_move(as, dst, src) \
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emit_ds(as, MIPSI_MOVE, (dst), (src))
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/* Generic move between two regs. */
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static void emit_movrr(ASMState *as, IRIns *ir, Reg dst, Reg src)
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{
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if (dst < RID_MAX_GPR)
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emit_move(as, dst, src);
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else
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emit_fg(as, irt_isnum(ir->t) ? MIPSI_MOV_D : MIPSI_MOV_S, dst, src);
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}
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/* Generic load of register with base and (small) offset address. */
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static void emit_loadofs(ASMState *as, IRIns *ir, Reg r, Reg base, int32_t ofs)
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{
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if (r < RID_MAX_GPR)
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emit_tsi(as, irt_is64(ir->t) ? MIPSI_LD : MIPSI_LW, r, base, ofs);
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else
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emit_tsi(as, irt_isnum(ir->t) ? MIPSI_LDC1 : MIPSI_LWC1,
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(r & 31), base, ofs);
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}
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/* Generic store of register with base and (small) offset address. */
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static void emit_storeofs(ASMState *as, IRIns *ir, Reg r, Reg base, int32_t ofs)
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{
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if (r < RID_MAX_GPR)
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emit_tsi(as, irt_is64(ir->t) ? MIPSI_SD : MIPSI_SW, r, base, ofs);
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else
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emit_tsi(as, irt_isnum(ir->t) ? MIPSI_SDC1 : MIPSI_SWC1,
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(r&31), base, ofs);
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}
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/* Add offset to pointer. */
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static void emit_addptr(ASMState *as, Reg r, int32_t ofs)
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{
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if (ofs) {
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lua_assert(checki16(ofs));
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emit_tsi(as, MIPSI_AADDIU, r, r, ofs);
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}
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}
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#define emit_spsub(as, ofs) emit_addptr(as, RID_SP, -(ofs))
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