mirror of https://github.com/odrling/Aegisub
420 lines
13 KiB
C
420 lines
13 KiB
C
/*
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** ARM64 instruction emitter.
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** Copyright (C) 2005-2017 Mike Pall. See Copyright Notice in luajit.h
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**
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** Contributed by Djordje Kovacevic and Stefan Pejic from RT-RK.com.
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** Sponsored by Cisco Systems, Inc.
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*/
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/* -- Constant encoding --------------------------------------------------- */
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static uint64_t get_k64val(IRIns *ir)
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{
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if (ir->o == IR_KINT64) {
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return ir_kint64(ir)->u64;
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} else if (ir->o == IR_KGC) {
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return (uint64_t)ir_kgc(ir);
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} else if (ir->o == IR_KPTR || ir->o == IR_KKPTR) {
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return (uint64_t)ir_kptr(ir);
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} else {
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lua_assert(ir->o == IR_KINT || ir->o == IR_KNULL);
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return ir->i; /* Sign-extended. */
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}
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}
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/* Encode constant in K12 format for data processing instructions. */
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static uint32_t emit_isk12(int64_t n)
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{
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uint64_t k = (n < 0) ? -n : n;
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uint32_t m = (n < 0) ? 0x40000000 : 0;
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if (k < 0x1000) {
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return A64I_K12|m|A64F_U12(k);
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} else if ((k & 0xfff000) == k) {
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return A64I_K12|m|0x400000|A64F_U12(k>>12);
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}
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return 0;
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}
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#define emit_clz64(n) __builtin_clzll(n)
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#define emit_ctz64(n) __builtin_ctzll(n)
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/* Encode constant in K13 format for logical data processing instructions. */
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static uint32_t emit_isk13(uint64_t n, int is64)
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{
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int inv = 0, w = 128, lz, tz;
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if (n & 1) { n = ~n; w = 64; inv = 1; } /* Avoid wrap-around of ones. */
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if (!n) return 0; /* Neither all-zero nor all-ones are allowed. */
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do { /* Find the repeat width. */
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if (is64 && (uint32_t)(n^(n>>32))) break;
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n = (uint32_t)n;
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if (!n) return 0; /* Ditto when passing n=0xffffffff and is64=0. */
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w = 32; if ((n^(n>>16)) & 0xffff) break;
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n = n & 0xffff; w = 16; if ((n^(n>>8)) & 0xff) break;
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n = n & 0xff; w = 8; if ((n^(n>>4)) & 0xf) break;
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n = n & 0xf; w = 4; if ((n^(n>>2)) & 0x3) break;
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n = n & 0x3; w = 2;
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} while (0);
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lz = emit_clz64(n);
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tz = emit_ctz64(n);
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if ((int64_t)(n << lz) >> (lz+tz) != -1ll) return 0; /* Non-contiguous? */
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if (inv)
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return A64I_K13 | (((lz-w) & 127) << 16) | (((lz+tz-w-1) & 63) << 10);
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else
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return A64I_K13 | ((w-tz) << 16) | (((63-lz-tz-w-w) & 63) << 10);
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}
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static uint32_t emit_isfpk64(uint64_t n)
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{
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uint64_t etop9 = ((n >> 54) & 0x1ff);
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if ((n << 16) == 0 && (etop9 == 0x100 || etop9 == 0x0ff)) {
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return (uint32_t)(((n >> 48) & 0x7f) | ((n >> 56) & 0x80));
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}
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return ~0u;
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}
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/* -- Emit basic instructions --------------------------------------------- */
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static void emit_dnma(ASMState *as, A64Ins ai, Reg rd, Reg rn, Reg rm, Reg ra)
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{
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*--as->mcp = ai | A64F_D(rd) | A64F_N(rn) | A64F_M(rm) | A64F_A(ra);
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}
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static void emit_dnm(ASMState *as, A64Ins ai, Reg rd, Reg rn, Reg rm)
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{
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*--as->mcp = ai | A64F_D(rd) | A64F_N(rn) | A64F_M(rm);
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}
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static void emit_dm(ASMState *as, A64Ins ai, Reg rd, Reg rm)
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{
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*--as->mcp = ai | A64F_D(rd) | A64F_M(rm);
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}
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static void emit_dn(ASMState *as, A64Ins ai, Reg rd, Reg rn)
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{
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*--as->mcp = ai | A64F_D(rd) | A64F_N(rn);
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}
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static void emit_nm(ASMState *as, A64Ins ai, Reg rn, Reg rm)
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{
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*--as->mcp = ai | A64F_N(rn) | A64F_M(rm);
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}
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static void emit_d(ASMState *as, A64Ins ai, Reg rd)
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{
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*--as->mcp = ai | A64F_D(rd);
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}
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static void emit_n(ASMState *as, A64Ins ai, Reg rn)
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{
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*--as->mcp = ai | A64F_N(rn);
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}
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static int emit_checkofs(A64Ins ai, int64_t ofs)
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{
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int scale = (ai >> 30) & 3;
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if (ofs < 0 || (ofs & ((1<<scale)-1))) {
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return (ofs >= -256 && ofs <= 255) ? -1 : 0;
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} else {
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return (ofs < (4096<<scale)) ? 1 : 0;
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}
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}
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static void emit_lso(ASMState *as, A64Ins ai, Reg rd, Reg rn, int64_t ofs)
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{
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int ot = emit_checkofs(ai, ofs), sc = (ai >> 30) & 3;
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lua_assert(ot);
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/* Combine LDR/STR pairs to LDP/STP. */
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if ((sc == 2 || sc == 3) &&
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(!(ai & 0x400000) || rd != rn) &&
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as->mcp != as->mcloop) {
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uint32_t prev = *as->mcp & ~A64F_D(31);
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int ofsm = ofs - (1<<sc), ofsp = ofs + (1<<sc);
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A64Ins aip;
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if (prev == (ai | A64F_N(rn) | A64F_U12(ofsm>>sc)) ||
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prev == ((ai^A64I_LS_U) | A64F_N(rn) | A64F_S9(ofsm&0x1ff))) {
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aip = (A64F_A(rd) | A64F_D(*as->mcp & 31));
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} else if (prev == (ai | A64F_N(rn) | A64F_U12(ofsp>>sc)) ||
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prev == ((ai^A64I_LS_U) | A64F_N(rn) | A64F_S9(ofsp&0x1ff))) {
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aip = (A64F_D(rd) | A64F_A(*as->mcp & 31));
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ofsm = ofs;
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} else {
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goto nopair;
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}
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if (ofsm >= (int)((unsigned int)-64<<sc) && ofsm <= (63<<sc)) {
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*as->mcp = aip | A64F_N(rn) | ((ofsm >> sc) << 15) |
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(ai ^ ((ai == A64I_LDRx || ai == A64I_STRx) ? 0x50000000 : 0x90000000));
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return;
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}
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}
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nopair:
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if (ot == 1)
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*--as->mcp = ai | A64F_D(rd) | A64F_N(rn) | A64F_U12(ofs >> sc);
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else
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*--as->mcp = (ai^A64I_LS_U) | A64F_D(rd) | A64F_N(rn) | A64F_S9(ofs & 0x1ff);
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}
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/* -- Emit loads/stores --------------------------------------------------- */
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/* Prefer rematerialization of BASE/L from global_State over spills. */
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#define emit_canremat(ref) ((ref) <= ASMREF_L)
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/* Try to find an N-step delta relative to other consts with N < lim. */
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static int emit_kdelta(ASMState *as, Reg rd, uint64_t k, int lim)
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{
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RegSet work = ~as->freeset & RSET_GPR;
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if (lim <= 1) return 0; /* Can't beat that. */
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while (work) {
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Reg r = rset_picktop(work);
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IRRef ref = regcost_ref(as->cost[r]);
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lua_assert(r != rd);
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if (ref < REF_TRUE) {
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uint64_t kx = ra_iskref(ref) ? (uint64_t)ra_krefk(as, ref) :
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get_k64val(IR(ref));
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int64_t delta = (int64_t)(k - kx);
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if (delta == 0) {
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emit_dm(as, A64I_MOVx, rd, r);
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return 1;
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} else {
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uint32_t k12 = emit_isk12(delta < 0 ? -delta : delta);
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if (k12) {
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emit_dn(as, (delta < 0 ? A64I_SUBx : A64I_ADDx)^k12, rd, r);
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return 1;
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}
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/* Do other ops or multi-step deltas pay off? Probably not.
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** E.g. XOR rarely helps with pointer consts.
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*/
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}
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}
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rset_clear(work, r);
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}
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return 0; /* Failed. */
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}
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static void emit_loadk(ASMState *as, Reg rd, uint64_t u64, int is64)
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{
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uint32_t k13 = emit_isk13(u64, is64);
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if (k13) { /* Can the constant be represented as a bitmask immediate? */
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emit_dn(as, (is64|A64I_ORRw)^k13, rd, RID_ZERO);
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} else {
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int i, zeros = 0, ones = 0, neg;
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if (!is64) u64 = (int64_t)(int32_t)u64; /* Sign-extend. */
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/* Count homogeneous 16 bit fragments. */
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for (i = 0; i < 4; i++) {
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uint64_t frag = (u64 >> i*16) & 0xffff;
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zeros += (frag == 0);
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ones += (frag == 0xffff);
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}
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neg = ones > zeros; /* Use MOVN if it pays off. */
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if (!emit_kdelta(as, rd, u64, 4 - (neg ? ones : zeros))) {
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int shift = 0, lshift = 0;
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uint64_t n64 = neg ? ~u64 : u64;
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if (n64 != 0) {
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/* Find first/last fragment to be filled. */
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shift = (63-emit_clz64(n64)) & ~15;
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lshift = emit_ctz64(n64) & ~15;
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}
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/* MOVK requires the original value (u64). */
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while (shift > lshift) {
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uint32_t u16 = (u64 >> shift) & 0xffff;
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/* Skip fragments that are correctly filled by MOVN/MOVZ. */
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if (u16 != (neg ? 0xffff : 0))
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emit_d(as, is64 | A64I_MOVKw | A64F_U16(u16) | A64F_LSL16(shift), rd);
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shift -= 16;
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}
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/* But MOVN needs an inverted value (n64). */
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emit_d(as, (neg ? A64I_MOVNx : A64I_MOVZx) |
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A64F_U16((n64 >> lshift) & 0xffff) | A64F_LSL16(lshift), rd);
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}
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}
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}
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/* Load a 32 bit constant into a GPR. */
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#define emit_loadi(as, rd, i) emit_loadk(as, rd, i, 0)
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/* Load a 64 bit constant into a GPR. */
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#define emit_loadu64(as, rd, i) emit_loadk(as, rd, i, A64I_X)
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#define emit_loada(as, r, addr) emit_loadu64(as, (r), (uintptr_t)(addr))
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#define glofs(as, k) \
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((intptr_t)((uintptr_t)(k) - (uintptr_t)&J2GG(as->J)->g))
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#define mcpofs(as, k) \
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((intptr_t)((uintptr_t)(k) - (uintptr_t)(as->mcp - 1)))
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#define checkmcpofs(as, k) \
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((((mcpofs(as, k)>>2) + 0x00040000) >> 19) == 0)
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static Reg ra_allock(ASMState *as, intptr_t k, RegSet allow);
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/* Get/set from constant pointer. */
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static void emit_lsptr(ASMState *as, A64Ins ai, Reg r, void *p)
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{
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/* First, check if ip + offset is in range. */
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if ((ai & 0x00400000) && checkmcpofs(as, p)) {
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emit_d(as, A64I_LDRLx | A64F_S19(mcpofs(as, p)>>2), r);
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} else {
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Reg base = RID_GL; /* Next, try GL + offset. */
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int64_t ofs = glofs(as, p);
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if (!emit_checkofs(ai, ofs)) { /* Else split up into base reg + offset. */
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int64_t i64 = i64ptr(p);
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base = ra_allock(as, (i64 & ~0x7fffull), rset_exclude(RSET_GPR, r));
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ofs = i64 & 0x7fffull;
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}
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emit_lso(as, ai, r, base, ofs);
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}
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}
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/* Load 64 bit IR constant into register. */
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static void emit_loadk64(ASMState *as, Reg r, IRIns *ir)
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{
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const uint64_t *k = &ir_k64(ir)->u64;
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int64_t ofs;
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if (r >= RID_MAX_GPR) {
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uint32_t fpk = emit_isfpk64(*k);
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if (fpk != ~0u) {
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emit_d(as, A64I_FMOV_DI | A64F_FP8(fpk), (r & 31));
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return;
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}
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}
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ofs = glofs(as, k);
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if (emit_checkofs(A64I_LDRx, ofs)) {
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emit_lso(as, r >= RID_MAX_GPR ? A64I_LDRd : A64I_LDRx,
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(r & 31), RID_GL, ofs);
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} else {
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if (r >= RID_MAX_GPR) {
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emit_dn(as, A64I_FMOV_D_R, (r & 31), RID_TMP);
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r = RID_TMP;
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}
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if (checkmcpofs(as, k))
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emit_d(as, A64I_LDRLx | A64F_S19(mcpofs(as, k)>>2), r);
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else
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emit_loadu64(as, r, *k);
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}
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}
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/* Get/set global_State fields. */
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#define emit_getgl(as, r, field) \
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emit_lsptr(as, A64I_LDRx, (r), (void *)&J2G(as->J)->field)
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#define emit_setgl(as, r, field) \
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emit_lsptr(as, A64I_STRx, (r), (void *)&J2G(as->J)->field)
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/* Trace number is determined from pc of exit instruction. */
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#define emit_setvmstate(as, i) UNUSED(i)
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/* -- Emit control-flow instructions -------------------------------------- */
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/* Label for internal jumps. */
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typedef MCode *MCLabel;
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/* Return label pointing to current PC. */
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#define emit_label(as) ((as)->mcp)
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static void emit_cond_branch(ASMState *as, A64CC cond, MCode *target)
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{
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MCode *p = --as->mcp;
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ptrdiff_t delta = target - p;
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lua_assert(((delta + 0x40000) >> 19) == 0);
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*p = A64I_BCC | A64F_S19(delta) | cond;
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}
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static void emit_branch(ASMState *as, A64Ins ai, MCode *target)
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{
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MCode *p = --as->mcp;
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ptrdiff_t delta = target - p;
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lua_assert(((delta + 0x02000000) >> 26) == 0);
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*p = ai | ((uint32_t)delta & 0x03ffffffu);
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}
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static void emit_tnb(ASMState *as, A64Ins ai, Reg r, uint32_t bit, MCode *target)
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{
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MCode *p = --as->mcp;
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ptrdiff_t delta = target - p;
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lua_assert(bit < 63 && ((delta + 0x2000) >> 14) == 0);
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if (bit > 31) ai |= A64I_X;
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*p = ai | A64F_BIT(bit & 31) | A64F_S14((uint32_t)delta & 0x3fffu) | r;
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}
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static void emit_cnb(ASMState *as, A64Ins ai, Reg r, MCode *target)
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{
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MCode *p = --as->mcp;
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ptrdiff_t delta = target - p;
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lua_assert(((delta + 0x40000) >> 19) == 0);
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*p = ai | A64F_S19(delta) | r;
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}
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#define emit_jmp(as, target) emit_branch(as, A64I_B, (target))
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static void emit_call(ASMState *as, void *target)
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{
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MCode *p = --as->mcp;
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ptrdiff_t delta = (char *)target - (char *)p;
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if ((((delta>>2) + 0x02000000) >> 26) == 0) {
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*p = A64I_BL | ((uint32_t)(delta>>2) & 0x03ffffffu);
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} else { /* Target out of range: need indirect call. But don't use R0-R7. */
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Reg r = ra_allock(as, i64ptr(target),
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RSET_RANGE(RID_X8, RID_MAX_GPR)-RSET_FIXED);
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*p = A64I_BLR | A64F_N(r);
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}
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}
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/* -- Emit generic operations --------------------------------------------- */
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/* Generic move between two regs. */
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static void emit_movrr(ASMState *as, IRIns *ir, Reg dst, Reg src)
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{
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if (dst >= RID_MAX_GPR) {
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emit_dn(as, irt_isnum(ir->t) ? A64I_FMOV_D : A64I_FMOV_S,
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(dst & 31), (src & 31));
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return;
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}
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if (as->mcp != as->mcloop) { /* Swap early registers for loads/stores. */
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MCode ins = *as->mcp, swp = (src^dst);
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if ((ins & 0xbf800000) == 0xb9000000) {
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if (!((ins ^ (dst << 5)) & 0x000003e0))
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*as->mcp = ins ^ (swp << 5); /* Swap N in load/store. */
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if (!(ins & 0x00400000) && !((ins ^ dst) & 0x0000001f))
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*as->mcp = ins ^ swp; /* Swap D in store. */
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}
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}
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emit_dm(as, A64I_MOVx, dst, src);
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}
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/* Generic load of register with base and (small) offset address. */
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static void emit_loadofs(ASMState *as, IRIns *ir, Reg r, Reg base, int32_t ofs)
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{
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if (r >= RID_MAX_GPR)
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emit_lso(as, irt_isnum(ir->t) ? A64I_LDRd : A64I_LDRs, (r & 31), base, ofs);
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else
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emit_lso(as, irt_is64(ir->t) ? A64I_LDRx : A64I_LDRw, r, base, ofs);
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}
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/* Generic store of register with base and (small) offset address. */
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static void emit_storeofs(ASMState *as, IRIns *ir, Reg r, Reg base, int32_t ofs)
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{
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if (r >= RID_MAX_GPR)
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emit_lso(as, irt_isnum(ir->t) ? A64I_STRd : A64I_STRs, (r & 31), base, ofs);
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else
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emit_lso(as, irt_is64(ir->t) ? A64I_STRx : A64I_STRw, r, base, ofs);
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}
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/* Emit an arithmetic operation with a constant operand. */
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static void emit_opk(ASMState *as, A64Ins ai, Reg dest, Reg src,
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int32_t i, RegSet allow)
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{
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uint32_t k = emit_isk12(i);
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if (k)
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emit_dn(as, ai^k, dest, src);
|
|
else
|
|
emit_dnm(as, ai, dest, src, ra_allock(as, i, allow));
|
|
}
|
|
|
|
/* Add offset to pointer. */
|
|
static void emit_addptr(ASMState *as, Reg r, int32_t ofs)
|
|
{
|
|
if (ofs)
|
|
emit_opk(as, ofs < 0 ? A64I_SUBx : A64I_ADDx, r, r,
|
|
ofs < 0 ? -ofs : ofs, rset_exclude(RSET_GPR, r));
|
|
}
|
|
|
|
#define emit_spsub(as, ofs) emit_addptr(as, RID_SP, -(ofs))
|
|
|