819 lines
26 KiB
C
819 lines
26 KiB
C
/*
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* Emulation of priviledged instructions
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*
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* Copyright 1995 Alexandre Julliard
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*/
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#include "wine/winuser16.h"
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#include "ldt.h"
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#include "global.h"
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#include "module.h"
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#include "dosexe.h"
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#include "miscemu.h"
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#include "sig_context.h"
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#include "selectors.h"
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#include "debugtools.h"
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DECLARE_DEBUG_CHANNEL(int)
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DECLARE_DEBUG_CHANNEL(io)
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#ifdef __i386__
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#define IS_V86(context) (EFL_sig(context)&V86_FLAG)
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#define IS_SEL_32(context,seg) \
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(IS_V86(context) ? FALSE : IS_SELECTOR_32BIT(seg))
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#define STACK_sig(context) \
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(IS_SEL_32(context,SS_sig(context)) ? ESP_sig(context) : (DWORD)SP_sig(context))
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#define ADD_STACK_sig(context,offset) \
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do { if (IS_SEL_32(context,SS_sig(context))) ESP_sig(context) += (offset); \
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else SP_sig(context) += (offset); } while(0)
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#define MAKE_PTR(seg,off) \
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(IS_SELECTOR_SYSTEM(seg) ? (void *)(off) : PTR_SEG_OFF_TO_LIN(seg,off))
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#define MK_PTR(context,seg,off) \
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(IS_V86(context) ? DOSMEM_MapRealToLinear(MAKELONG(off,seg)) \
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: MAKE_PTR(seg,off))
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#define STACK_PTR(context) \
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(IS_V86(context) ? DOSMEM_MapRealToLinear(MAKELONG(SP_sig(context),SS_sig(context))) : \
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(IS_SELECTOR_SYSTEM(SS_sig(context)) ? (void *)ESP_sig(context) : \
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(PTR_SEG_OFF_TO_LIN(SS_sig(context),STACK_sig(context)))))
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/***********************************************************************
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* INSTR_ReplaceSelector
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*
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* Try to replace an invalid selector by a valid one.
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* The only selector where it is allowed to do "mov ax,40;mov es,ax"
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* is the so called 'bimodal' selector 0x40, which points to the BIOS
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* data segment. Used by (at least) Borland products (and programs compiled
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* using Borland products).
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*
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* See Undocumented Windows, Chapter 5, __0040.
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*/
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static BOOL INSTR_ReplaceSelector( SIGCONTEXT *context, WORD *sel )
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{
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extern char Call16_Start, Call16_End;
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if (IS_SELECTOR_SYSTEM(CS_sig(context)))
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if ( (char *)EIP_sig(context) >= &Call16_Start
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&& (char *)EIP_sig(context) < &Call16_End )
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{
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/* Saved selector may have become invalid when the relay code */
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/* tries to restore it. We simply clear it. */
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*sel = 0;
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return TRUE;
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}
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if (*sel == 0x40)
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{
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static WORD sys_timer = 0;
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if (!sys_timer)
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sys_timer = CreateSystemTimer( 55, DOSMEM_Tick );
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*sel = DOSMEM_BiosDataSeg;
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return TRUE;
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}
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if (!IS_SELECTOR_SYSTEM(*sel) && !IS_SELECTOR_FREE(*sel))
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ERR_(int)("Got protection fault on valid selector, maybe your kernel is too old?\n" );
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return FALSE; /* Can't replace selector, crashdump */
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}
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/***********************************************************************
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* INSTR_GetOperandAddr
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*
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* Return the address of an instruction operand (from the mod/rm byte).
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*/
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static BYTE *INSTR_GetOperandAddr( SIGCONTEXT *context, BYTE *instr,
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int long_addr, int segprefix, int *len )
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{
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int mod, rm, base, index = 0, ss = 0, seg = 0, off;
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#define GET_VAL(val,type) \
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{ *val = *(type *)instr; instr += sizeof(type); *len += sizeof(type); }
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*len = 0;
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GET_VAL( &mod, BYTE );
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rm = mod & 7;
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mod >>= 6;
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if (mod == 3)
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{
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switch(rm)
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{
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case 0: return (BYTE *)&EAX_sig(context);
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case 1: return (BYTE *)&ECX_sig(context);
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case 2: return (BYTE *)&EDX_sig(context);
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case 3: return (BYTE *)&EBX_sig(context);
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case 4: return (BYTE *)&ESP_sig(context);
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case 5: return (BYTE *)&EBP_sig(context);
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case 6: return (BYTE *)&ESI_sig(context);
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case 7: return (BYTE *)&EDI_sig(context);
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}
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}
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if (long_addr)
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{
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if (rm == 4)
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{
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BYTE sib;
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GET_VAL( &sib, BYTE );
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rm = sib & 7;
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ss = sib >> 6;
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switch(sib >> 3)
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{
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case 0: index = EAX_sig(context); break;
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case 1: index = ECX_sig(context); break;
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case 2: index = EDX_sig(context); break;
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case 3: index = EBX_sig(context); break;
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case 4: index = 0; break;
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case 5: index = EBP_sig(context); break;
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case 6: index = ESI_sig(context); break;
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case 7: index = EDI_sig(context); break;
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}
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}
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switch(rm)
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{
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case 0: base = EAX_sig(context); seg = DS_sig(context); break;
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case 1: base = ECX_sig(context); seg = DS_sig(context); break;
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case 2: base = EDX_sig(context); seg = DS_sig(context); break;
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case 3: base = EBX_sig(context); seg = DS_sig(context); break;
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case 4: base = ESP_sig(context); seg = SS_sig(context); break;
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case 5: base = EBP_sig(context); seg = SS_sig(context); break;
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case 6: base = ESI_sig(context); seg = DS_sig(context); break;
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case 7: base = EDI_sig(context); seg = DS_sig(context); break;
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}
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switch (mod)
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{
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case 0:
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if (rm == 5) /* special case: ds:(disp32) */
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{
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GET_VAL( &base, DWORD );
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seg = DS_sig(context);
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}
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break;
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case 1: /* 8-bit disp */
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GET_VAL( &off, BYTE );
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base += (signed char)off;
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break;
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case 2: /* 32-bit disp */
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GET_VAL( &off, DWORD );
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base += (signed long)off;
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break;
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}
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}
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else /* short address */
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{
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switch(rm)
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{
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case 0: /* ds:(bx,si) */
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base = BX_sig(context) + SI_sig(context);
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seg = DS_sig(context);
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break;
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case 1: /* ds:(bx,di) */
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base = BX_sig(context) + DI_sig(context);
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seg = DS_sig(context);
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break;
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case 2: /* ss:(bp,si) */
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base = BP_sig(context) + SI_sig(context);
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seg = SS_sig(context);
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break;
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case 3: /* ss:(bp,di) */
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base = BP_sig(context) + DI_sig(context);
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seg = SS_sig(context);
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break;
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case 4: /* ds:(si) */
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base = SI_sig(context);
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seg = DS_sig(context);
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break;
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case 5: /* ds:(di) */
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base = DI_sig(context);
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seg = DS_sig(context);
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break;
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case 6: /* ss:(bp) */
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base = BP_sig(context);
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seg = SS_sig(context);
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break;
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case 7: /* ds:(bx) */
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base = BX_sig(context);
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seg = DS_sig(context);
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break;
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}
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switch(mod)
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{
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case 0:
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if (rm == 6) /* special case: ds:(disp16) */
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{
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GET_VAL( &base, WORD );
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seg = DS_sig(context);
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}
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break;
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case 1: /* 8-bit disp */
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GET_VAL( &off, BYTE );
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base += (signed char)off;
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break;
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case 2: /* 16-bit disp */
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GET_VAL( &off, WORD );
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base += (signed short)off;
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break;
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}
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base &= 0xffff;
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}
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if (segprefix != -1) seg = segprefix;
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/* Make sure the segment and offset are valid */
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if (IS_SELECTOR_SYSTEM(seg)) return (BYTE *)(base + (index << ss));
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if (((seg & 7) != 7) || IS_SELECTOR_FREE(seg)) return NULL;
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if (GET_SEL_LIMIT(seg) < (base + (index << ss))) return NULL;
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return (BYTE *)PTR_SEG_OFF_TO_LIN( seg, (base + (index << ss)) );
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#undef GET_VAL
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}
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/***********************************************************************
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* INSTR_EmulateLDS
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*
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* Emulate the LDS (and LES,LFS,etc.) instruction.
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*/
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static BOOL INSTR_EmulateLDS( SIGCONTEXT *context, BYTE *instr, int long_op,
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int long_addr, int segprefix, int *len )
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{
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WORD seg;
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BYTE *regmodrm = instr + 1 + (*instr == 0x0f);
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BYTE *addr = INSTR_GetOperandAddr( context, regmodrm,
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long_addr, segprefix, len );
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if (!addr)
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return FALSE; /* Unable to emulate it */
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seg = *(WORD *)(addr + (long_op ? 4 : 2));
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if (!INSTR_ReplaceSelector( context, &seg ))
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return FALSE; /* Unable to emulate it */
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/* Now store the offset in the correct register */
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switch((*regmodrm >> 3) & 7)
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{
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case 0:
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if (long_op) EAX_sig(context) = *(DWORD *)addr;
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else AX_sig(context) = *(WORD *)addr;
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break;
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case 1:
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if (long_op) ECX_sig(context) = *(DWORD *)addr;
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else CX_sig(context) = *(WORD *)addr;
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break;
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case 2:
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if (long_op) EDX_sig(context) = *(DWORD *)addr;
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else DX_sig(context) = *(WORD *)addr;
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break;
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case 3:
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if (long_op) EBX_sig(context) = *(DWORD *)addr;
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else BX_sig(context) = *(WORD *)addr;
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break;
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case 4:
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if (long_op) ESP_sig(context) = *(DWORD *)addr;
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else SP_sig(context) = *(WORD *)addr;
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break;
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case 5:
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if (long_op) EBP_sig(context) = *(DWORD *)addr;
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else BP_sig(context) = *(WORD *)addr;
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break;
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case 6:
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if (long_op) ESI_sig(context) = *(DWORD *)addr;
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else SI_sig(context) = *(WORD *)addr;
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break;
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case 7:
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if (long_op) EDI_sig(context) = *(DWORD *)addr;
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else DI_sig(context) = *(WORD *)addr;
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break;
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}
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/* Store the correct segment in the segment register */
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switch(*instr)
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{
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case 0xc4: ES_sig(context) = seg; break; /* les */
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case 0xc5: DS_sig(context) = seg; break; /* lds */
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case 0x0f: switch(instr[1])
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{
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case 0xb2: SS_sig(context) = seg; break; /* lss */
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#ifdef FS_sig
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case 0xb4: FS_sig(context) = seg; break; /* lfs */
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#endif
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#ifdef GS_sig
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case 0xb5: GS_sig(context) = seg; break; /* lgs */
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#endif
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}
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break;
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}
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/* Add the opcode size to the total length */
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*len += 1 + (*instr == 0x0f);
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return TRUE;
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}
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/***********************************************************************
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* INSTR_EmulateInstruction
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*
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* Emulate a priviledged instruction. Returns TRUE if emulation successful.
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*/
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BOOL INSTR_EmulateInstruction( SIGCONTEXT *context )
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{
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int prefix, segprefix, prefixlen, len, repX, long_op, long_addr;
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SEGPTR gpHandler;
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BYTE *instr;
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long_op = long_addr = IS_SEL_32(context,CS_sig(context));
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instr = (BYTE *)MK_PTR(context,CS_sig(context),EIP_sig(context));
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if (!instr) return FALSE;
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/* First handle any possible prefix */
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segprefix = -1; /* no prefix */
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prefix = 1;
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repX = 0;
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prefixlen = 0;
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while(prefix)
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{
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switch(*instr)
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{
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case 0x2e:
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segprefix = CS_sig(context);
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break;
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case 0x36:
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segprefix = SS_sig(context);
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break;
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case 0x3e:
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segprefix = DS_sig(context);
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break;
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case 0x26:
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segprefix = ES_sig(context);
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break;
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#ifdef FS_sig
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case 0x64:
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segprefix = FS_sig(context);
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break;
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#endif
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#ifdef GS_sig
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case 0x65:
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segprefix = GS_sig(context);
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break;
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#endif
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case 0x66:
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long_op = !long_op; /* opcode size prefix */
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break;
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case 0x67:
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long_addr = !long_addr; /* addr size prefix */
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break;
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case 0xf0: /* lock */
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break;
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case 0xf2: /* repne */
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repX = 1;
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break;
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case 0xf3: /* repe */
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repX = 2;
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break;
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default:
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prefix = 0; /* no more prefixes */
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break;
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}
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if (prefix)
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{
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instr++;
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prefixlen++;
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}
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}
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/* Now look at the actual instruction */
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switch(*instr)
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{
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case 0x07: /* pop es */
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case 0x17: /* pop ss */
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case 0x1f: /* pop ds */
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{
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WORD seg = *(WORD *)STACK_PTR( context );
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if (INSTR_ReplaceSelector( context, &seg ))
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{
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switch(*instr)
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{
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case 0x07: ES_sig(context) = seg; break;
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case 0x17: SS_sig(context) = seg; break;
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case 0x1f: DS_sig(context) = seg; break;
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}
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ADD_STACK_sig(context, long_op ? 4 : 2);
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EIP_sig(context) += prefixlen + 1;
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return TRUE;
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}
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}
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break; /* Unable to emulate it */
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case 0x0f: /* extended instruction */
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switch(instr[1])
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{
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case 0x22: /* mov eax, crX */
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switch (instr[2]) {
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case 0xc0:
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fprintf(stderr,"mov eax,cr0 at 0x%08lx, EAX=0x%08lx\n",
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EIP_sig(context),EAX_sig(context)
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);
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EIP_sig(context) += prefixlen+3;
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return TRUE;
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default:
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break; /*fallthrough to bad instruction handling */
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}
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break; /*fallthrough to bad instruction handling */
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case 0x20: /* mov crX, eax */
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switch (instr[2]) {
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case 0xe0: /* mov cr4, eax */
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/* CR4 register . See linux/arch/i386/mm/init.c, X86_CR4_ defs
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* bit 0: VME Virtual Mode Exception ?
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* bit 1: PVI Protected mode Virtual Interrupt
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* bit 2: TSD Timestamp disable
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* bit 3: DE Debugging extensions
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* bit 4: PSE Page size extensions
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* bit 5: PAE Physical address extension
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* bit 6: MCE Machine check enable
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* bit 7: PGE Enable global pages
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* bit 8: PCE Enable performance counters at IPL3
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*/
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fprintf(stderr,"mov cr4,eax at 0x%08lx\n",EIP_sig(context));
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EAX_sig(context) = 0;
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EIP_sig(context) += prefixlen+3;
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return TRUE;
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case 0xc0: /* mov cr0, eax */
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fprintf(stderr,"mov cr0,eax at 0x%08lx\n",EIP_sig(context));
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EAX_sig(context) = 0x10; /* FIXME: set more bits ? */
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EIP_sig(context) += prefixlen+3;
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return TRUE;
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default: /* fallthrough to illegal instruction */
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break;
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}
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/* fallthrough to illegal instruction */
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break;
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#ifdef FS_sig
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case 0xa1: /* pop fs */
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{
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WORD seg = *(WORD *)STACK_PTR( context );
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if (INSTR_ReplaceSelector( context, &seg ))
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{
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FS_sig(context) = seg;
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ADD_STACK_sig(context, long_op ? 4 : 2);
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EIP_sig(context) += prefixlen + 2;
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return TRUE;
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}
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}
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break;
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#endif /* FS_sig */
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#ifdef GS_sig
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case 0xa9: /* pop gs */
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{
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WORD seg = *(WORD *)STACK_PTR( context );
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if (INSTR_ReplaceSelector( context, &seg ))
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{
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GS_sig(context) = seg;
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ADD_STACK_sig(context, long_op ? 4 : 2);
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EIP_sig(context) += prefixlen + 2;
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return TRUE;
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}
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}
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break;
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#endif /* GS_sig */
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case 0xb2: /* lss addr,reg */
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#ifdef FS_sig
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case 0xb4: /* lfs addr,reg */
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#endif
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#ifdef GS_sig
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case 0xb5: /* lgs addr,reg */
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#endif
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if (INSTR_EmulateLDS( context, instr, long_op,
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long_addr, segprefix, &len ))
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{
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EIP_sig(context) += prefixlen + len;
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return TRUE;
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}
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break;
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}
|
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break; /* Unable to emulate it */
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case 0x6c: /* insb */
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case 0x6d: /* insw/d */
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case 0x6e: /* outsb */
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case 0x6f: /* outsw/d */
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{
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int typ = *instr; /* Just in case it's overwritten. */
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|
int outp = (typ >= 0x6e);
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unsigned long count = repX ?
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(long_addr ? ECX_sig(context) : CX_sig(context)) : 1;
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|
int opsize = (typ & 1) ? (long_op ? 4 : 2) : 1;
|
|
int step = (EFL_sig(context) & 0x400) ? -opsize : +opsize;
|
|
int seg = outp ? DS_sig(context) : ES_sig(context); /* FIXME: is this right? */
|
|
|
|
if (outp)
|
|
/* FIXME: Check segment readable. */
|
|
(void)0;
|
|
else
|
|
/* FIXME: Check segment writeable. */
|
|
(void)0;
|
|
|
|
if (repX)
|
|
{
|
|
if (long_addr)
|
|
ECX_sig(context) = 0;
|
|
else
|
|
CX_sig(context) = 0;
|
|
}
|
|
|
|
while (count-- > 0)
|
|
{
|
|
void *data;
|
|
if (outp)
|
|
{
|
|
data = MK_PTR(context, seg,
|
|
long_addr ? ESI_sig(context) : SI_sig(context));
|
|
if (long_addr) ESI_sig(context) += step;
|
|
else SI_sig(context) += step;
|
|
}
|
|
else
|
|
{
|
|
data = MK_PTR(context, seg,
|
|
long_addr ? EDI_sig(context) : DI_sig(context));
|
|
if (long_addr) EDI_sig(context) += step;
|
|
else DI_sig(context) += step;
|
|
}
|
|
|
|
switch (typ)
|
|
{
|
|
case 0x6c:
|
|
*((BYTE *)data) = IO_inport( DX_sig(context), 1);
|
|
TRACE_(io)("0x%x < %02x @ %04x:%04x\n", DX_sig(context),
|
|
*((BYTE *)data), CS_sig(context), IP_sig(context));
|
|
break;
|
|
case 0x6d:
|
|
if (long_op)
|
|
{
|
|
*((DWORD *)data) = IO_inport( DX_sig(context), 4);
|
|
TRACE_(io)("0x%x < %08lx @ %04x:%04x\n", DX_sig(context),
|
|
*((DWORD *)data), CS_sig(context), IP_sig(context));
|
|
}
|
|
else
|
|
{
|
|
*((WORD *)data) = IO_inport( DX_sig(context), 2);
|
|
TRACE_(io)("0x%x < %04x @ %04x:%04x\n", DX_sig(context),
|
|
*((WORD *)data), CS_sig(context), IP_sig(context));
|
|
}
|
|
break;
|
|
case 0x6e:
|
|
IO_outport( DX_sig(context), 1, *((BYTE *)data));
|
|
TRACE_(io)("0x%x > %02x @ %04x:%04x\n", DX_sig(context),
|
|
*((BYTE *)data), CS_sig(context), IP_sig(context));
|
|
break;
|
|
case 0x6f:
|
|
if (long_op)
|
|
{
|
|
IO_outport( DX_sig(context), 4, *((DWORD *)data));
|
|
TRACE_(io)("0x%x > %08lx @ %04x:%04x\n", DX_sig(context),
|
|
*((DWORD *)data), CS_sig(context), IP_sig(context));
|
|
}
|
|
else
|
|
{
|
|
IO_outport( DX_sig(context), 2, *((WORD *)data));
|
|
TRACE_(io)("0x%x > %04x @ %04x:%04x\n", DX_sig(context),
|
|
*((WORD *)data), CS_sig(context), IP_sig(context));
|
|
}
|
|
break;
|
|
}
|
|
}
|
|
EIP_sig(context) += prefixlen + 1;
|
|
}
|
|
return TRUE;
|
|
|
|
case 0x8e: /* mov XX,segment_reg */
|
|
{
|
|
WORD seg;
|
|
BYTE *addr = INSTR_GetOperandAddr(context, instr + 1,
|
|
long_addr, segprefix, &len );
|
|
if (!addr)
|
|
break; /* Unable to emulate it */
|
|
seg = *(WORD *)addr;
|
|
if (!INSTR_ReplaceSelector( context, &seg ))
|
|
break; /* Unable to emulate it */
|
|
|
|
switch((instr[1] >> 3) & 7)
|
|
{
|
|
case 0:
|
|
ES_sig(context) = seg;
|
|
EIP_sig(context) += prefixlen + len + 1;
|
|
return TRUE;
|
|
case 1: /* cs */
|
|
break;
|
|
case 2:
|
|
SS_sig(context) = seg;
|
|
EIP_sig(context) += prefixlen + len + 1;
|
|
return TRUE;
|
|
case 3:
|
|
DS_sig(context) = seg;
|
|
EIP_sig(context) += prefixlen + len + 1;
|
|
return TRUE;
|
|
#ifdef FS_sig
|
|
case 4:
|
|
FS_sig(context) = seg;
|
|
EIP_sig(context) += prefixlen + len + 1;
|
|
return TRUE;
|
|
#endif
|
|
#ifdef GS_sig
|
|
case 5:
|
|
GS_sig(context) = seg;
|
|
EIP_sig(context) += prefixlen + len + 1;
|
|
return TRUE;
|
|
#endif
|
|
case 6: /* unused */
|
|
case 7: /* unused */
|
|
break;
|
|
}
|
|
}
|
|
break; /* Unable to emulate it */
|
|
|
|
case 0xc4: /* les addr,reg */
|
|
case 0xc5: /* lds addr,reg */
|
|
if (INSTR_EmulateLDS( context, instr, long_op,
|
|
long_addr, segprefix, &len ))
|
|
{
|
|
EIP_sig(context) += prefixlen + len;
|
|
return TRUE;
|
|
}
|
|
break; /* Unable to emulate it */
|
|
|
|
case 0xcd: /* int <XX> */
|
|
if (long_op)
|
|
{
|
|
ERR_(int)("int xx from 32-bit code is not supported.\n");
|
|
break; /* Unable to emulate it */
|
|
}
|
|
else
|
|
{
|
|
FARPROC16 addr = INT_GetPMHandler( instr[1] );
|
|
WORD *stack = (WORD *)STACK_PTR( context );
|
|
/* Push the flags and return address on the stack */
|
|
*(--stack) = FL_sig(context);
|
|
*(--stack) = CS_sig(context);
|
|
*(--stack) = IP_sig(context) + prefixlen + 2;
|
|
ADD_STACK_sig(context, -3 * sizeof(WORD));
|
|
/* Jump to the interrupt handler */
|
|
CS_sig(context) = HIWORD(addr);
|
|
EIP_sig(context) = LOWORD(addr);
|
|
}
|
|
return TRUE;
|
|
|
|
case 0xcf: /* iret */
|
|
if (long_op)
|
|
{
|
|
DWORD *stack = (DWORD *)STACK_PTR( context );
|
|
EIP_sig(context) = *stack++;
|
|
CS_sig(context) = *stack++;
|
|
EFL_sig(context) = *stack;
|
|
ADD_STACK_sig(context, 3*sizeof(DWORD)); /* Pop the return address and flags */
|
|
}
|
|
else
|
|
{
|
|
WORD *stack = (WORD *)STACK_PTR( context );
|
|
EIP_sig(context) = *stack++;
|
|
CS_sig(context) = *stack++;
|
|
FL_sig(context) = *stack;
|
|
ADD_STACK_sig(context, 3*sizeof(WORD)); /* Pop the return address and flags */
|
|
}
|
|
return TRUE;
|
|
|
|
case 0xe4: /* inb al,XX */
|
|
AL_sig(context) = IO_inport( instr[1], 1 );
|
|
TRACE_(io)("0x%x < %02x @ %04x:%04x\n", instr[1],
|
|
AL_sig(context), CS_sig(context), IP_sig(context));
|
|
EIP_sig(context) += prefixlen + 2;
|
|
return TRUE;
|
|
|
|
case 0xe5: /* in (e)ax,XX */
|
|
if (long_op)
|
|
{
|
|
EAX_sig(context) = IO_inport( instr[1], 4 );
|
|
TRACE_(io)("0x%x < %08lx @ %04x:%04x\n", instr[1],
|
|
EAX_sig(context), CS_sig(context), IP_sig(context));
|
|
}
|
|
else
|
|
{
|
|
AX_sig(context) = IO_inport( instr[1], 2 );
|
|
TRACE_(io)("0x%x < %04x @ %04x:%04x\n", instr[1],
|
|
AX_sig(context), CS_sig(context), IP_sig(context));
|
|
}
|
|
EIP_sig(context) += prefixlen + 2;
|
|
return TRUE;
|
|
|
|
case 0xe6: /* outb XX,al */
|
|
IO_outport( instr[1], 1, AL_sig(context) );
|
|
TRACE_(io)("0x%x > %02x @ %04x:%04x\n", instr[1],
|
|
AL_sig(context), CS_sig(context), IP_sig(context));
|
|
EIP_sig(context) += prefixlen + 2;
|
|
return TRUE;
|
|
|
|
case 0xe7: /* out XX,(e)ax */
|
|
if (long_op)
|
|
{
|
|
IO_outport( instr[1], 4, EAX_sig(context) );
|
|
TRACE_(io)("0x%x > %08lx @ %04x:%04x\n", instr[1],
|
|
EAX_sig(context), CS_sig(context), IP_sig(context));
|
|
}
|
|
else
|
|
{
|
|
IO_outport( instr[1], 2, AX_sig(context) );
|
|
TRACE_(io)("0x%x > %04x @ %04x:%04x\n", instr[1],
|
|
AX_sig(context), CS_sig(context), IP_sig(context));
|
|
}
|
|
EIP_sig(context) += prefixlen + 2;
|
|
return TRUE;
|
|
|
|
case 0xec: /* inb al,dx */
|
|
AL_sig(context) = IO_inport( DX_sig(context), 1 );
|
|
TRACE_(io)("0x%x < %02x @ %04x:%04x\n", DX_sig(context),
|
|
AL_sig(context), CS_sig(context), IP_sig(context));
|
|
EIP_sig(context) += prefixlen + 1;
|
|
return TRUE;
|
|
|
|
case 0xed: /* in (e)ax,dx */
|
|
if (long_op)
|
|
{
|
|
EAX_sig(context) = IO_inport( DX_sig(context), 4 );
|
|
TRACE_(io)("0x%x < %08lx @ %04x:%04x\n", DX_sig(context),
|
|
EAX_sig(context), CS_sig(context), IP_sig(context));
|
|
}
|
|
else
|
|
{
|
|
AX_sig(context) = IO_inport( DX_sig(context), 2 );
|
|
TRACE_(io)("0x%x < %04x @ %04x:%04x\n", DX_sig(context),
|
|
AX_sig(context), CS_sig(context), IP_sig(context));
|
|
}
|
|
EIP_sig(context) += prefixlen + 1;
|
|
return TRUE;
|
|
|
|
case 0xee: /* outb dx,al */
|
|
IO_outport( DX_sig(context), 1, AL_sig(context) );
|
|
TRACE_(io)("0x%x > %02x @ %04x:%04x\n", DX_sig(context),
|
|
AL_sig(context), CS_sig(context), IP_sig(context));
|
|
EIP_sig(context) += prefixlen + 1;
|
|
return TRUE;
|
|
|
|
case 0xef: /* out dx,(e)ax */
|
|
if (long_op)
|
|
{
|
|
IO_outport( DX_sig(context), 4, EAX_sig(context) );
|
|
TRACE_(io)("0x%x > %08lx @ %04x:%04x\n", DX_sig(context),
|
|
EAX_sig(context), CS_sig(context), IP_sig(context));
|
|
}
|
|
else
|
|
{
|
|
IO_outport( DX_sig(context), 2, AX_sig(context) );
|
|
TRACE_(io)("0x%x > %04x @ %04x:%04x\n", DX_sig(context),
|
|
AX_sig(context), CS_sig(context), IP_sig(context));
|
|
}
|
|
EIP_sig(context) += prefixlen + 1;
|
|
return TRUE;
|
|
|
|
case 0xfa: /* cli, ignored */
|
|
EIP_sig(context) += prefixlen + 1;
|
|
return TRUE;
|
|
|
|
case 0xfb: /* sti, ignored */
|
|
EIP_sig(context) += prefixlen + 1;
|
|
return TRUE;
|
|
}
|
|
|
|
|
|
/* Check for Win16 __GP handler */
|
|
gpHandler = HasGPHandler16( PTR_SEG_OFF_TO_SEGPTR( CS_sig(context),
|
|
EIP_sig(context) ) );
|
|
if (gpHandler)
|
|
{
|
|
WORD *stack = (WORD *)STACK_PTR( context );
|
|
*--stack = CS_sig(context);
|
|
*--stack = EIP_sig(context);
|
|
ADD_STACK_sig(context, -2*sizeof(WORD));
|
|
|
|
CS_sig(context) = SELECTOROF( gpHandler );
|
|
EIP_sig(context) = OFFSETOF( gpHandler );
|
|
return TRUE;
|
|
}
|
|
return FALSE; /* Unable to emulate it */
|
|
}
|
|
|
|
#endif /* __i386__ */
|