1184 lines
32 KiB
C
1184 lines
32 KiB
C
/*
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* Emulation of processor ioports.
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*
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* Copyright 1995 Morten Welinder
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* Copyright 1998 Andreas Mohr, Ove Kaaven
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* Copyright 2001 Uwe Bonnes
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA
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*/
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/* Known problems:
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- only a few ports are emulated.
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- real-time clock in "cmos" is bogus. A nifty alarm() setup could
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fix that, I guess.
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*/
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#include "config.h"
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#include <stdarg.h>
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#include <stdlib.h>
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#include <sys/types.h>
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#ifdef HAVE_SYS_STAT_H
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# include <sys/stat.h>
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#endif
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#ifdef HAVE_PPDEV
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#include <fcntl.h>
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#include <errno.h>
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#ifdef HAVE_SYS_IOCTL_H
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# include <sys/ioctl.h>
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#endif
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#ifdef HAVE_LINUX_IOCTL_H
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# include <linux/ioctl.h>
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#endif
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#include <linux/ppdev.h>
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#endif
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#include "windef.h"
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#include "winbase.h"
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#include "winnls.h"
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#include "winreg.h"
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#include "winternl.h"
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#include "kernel16_private.h"
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#include "dosexe.h"
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#include "vga.h"
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#include "wine/unicode.h"
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#include "wine/debug.h"
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WINE_DEFAULT_DEBUG_CHANNEL(int);
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#if defined(linux) && !defined(__ANDROID__)
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# define DIRECT_IO_ACCESS
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#else
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# undef DIRECT_IO_ACCESS
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#endif
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static struct {
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WORD countmax;
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WORD latch;
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BYTE ctrlbyte_ch;
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BYTE flags;
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LONG64 start_time;
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} tmr_8253[3] = {
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{0xFFFF, 0, 0x36, 0, 0},
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{0x0012, 0, 0x74, 0, 0},
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{0x0001, 0, 0xB6, 0, 0},
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};
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/* two byte read in progress */
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#define TMR_RTOGGLE 0x01
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/* two byte write in progress */
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#define TMR_WTOGGLE 0x02
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/* latch contains data */
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#define TMR_LATCHED 0x04
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/* counter is in update phase */
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#define TMR_UPDATE 0x08
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/* readback status request */
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#define TMR_STATUS 0x10
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static BYTE parport_8255[4] = {0x4f, 0x20, 0xff, 0xff};
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static BYTE cmosaddress;
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static int cmos_image_initialized = 0;
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static BYTE cmosimage[64] =
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{
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0x27, /* 0x00: seconds */
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0x34, /* 0X01: seconds alarm */
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0x31, /* 0x02: minutes */
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0x47, /* 0x03: minutes alarm */
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0x16, /* 0x04: hour */
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0x15, /* 0x05: hour alarm */
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0x00, /* 0x06: week day */
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0x01, /* 0x07: month day */
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0x04, /* 0x08: month */
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0x94, /* 0x09: year */
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0x26, /* 0x0a: state A */
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0x02, /* 0x0b: state B */
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0x50, /* 0x0c: state C */
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0x80, /* 0x0d: state D */
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0x00, /* 0x0e: state diagnostic */
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0x00, /* 0x0f: state state shutdown */
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0x40, /* 0x10: floppy type */
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0xb1, /* 0x11: reserved */
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0x00, /* 0x12: HD type */
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0x9c, /* 0x13: reserved */
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0x01, /* 0x14: equipment */
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0x80, /* 0x15: low base memory */
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0x02, /* 0x16: high base memory (0x280 => 640KB) */
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0x00, /* 0x17: low extended memory */
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0x3b, /* 0x18: high extended memory (0x3b00 => 15MB) */
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0x00, /* 0x19: HD 1 extended type byte */
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0x00, /* 0x1a: HD 2 extended type byte */
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0xad, /* 0x1b: reserved */
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0x02, /* 0x1c: reserved */
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0x10, /* 0x1d: reserved */
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0x00, /* 0x1e: reserved */
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0x00, /* 0x1f: installed features */
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0x08, /* 0x20: HD 1 low cylinder number */
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0x00, /* 0x21: HD 1 high cylinder number */
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0x00, /* 0x22: HD 1 heads */
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0x26, /* 0x23: HD 1 low pre-compensation start */
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0x00, /* 0x24: HD 1 high pre-compensation start */
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0x00, /* 0x25: HD 1 low landing zone */
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0x00, /* 0x26: HD 1 high landing zone */
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0x00, /* 0x27: HD 1 sectors */
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0x00, /* 0x28: options 1 */
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0x00, /* 0x29: reserved */
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0x00, /* 0x2a: reserved */
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0x00, /* 0x2b: options 2 */
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0x00, /* 0x2c: options 3 */
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0x3f, /* 0x2d: reserved */
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0xcc, /* 0x2e: low CMOS ram checksum (computed automatically) */
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0xcc, /* 0x2f: high CMOS ram checksum (computed automatically) */
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0x00, /* 0x30: low extended memory byte */
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0x1c, /* 0x31: high extended memory byte */
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0x19, /* 0x32: century byte */
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0x81, /* 0x33: setup information */
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0x00, /* 0x34: CPU speed */
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0x0e, /* 0x35: HD 2 low cylinder number */
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0x00, /* 0x36: HD 2 high cylinder number */
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0x80, /* 0x37: HD 2 heads */
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0x1b, /* 0x38: HD 2 low pre-compensation start */
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0x7b, /* 0x39: HD 2 high pre-compensation start */
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0x21, /* 0x3a: HD 2 low landing zone */
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0x00, /* 0x3b: HD 2 high landing zone */
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0x00, /* 0x3c: HD 2 sectors */
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0x00, /* 0x3d: reserved */
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0x05, /* 0x3e: reserved */
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0x5f /* 0x3f: reserved */
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};
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static void IO_FixCMOSCheckSum(void)
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{
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WORD sum = 0;
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int i;
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for (i=0x10; i < 0x2d; i++)
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sum += cmosimage[i];
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cmosimage[0x2e] = sum >> 8; /* yes, this IS hi byte !! */
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cmosimage[0x2f] = sum & 0xff;
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TRACE("calculated hi %02x, lo %02x\n", cmosimage[0x2e], cmosimage[0x2f]);
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}
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#ifdef DIRECT_IO_ACCESS
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extern int iopl(int level);
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static char do_direct_port_access = -1;
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static char port_permissions[0x10000];
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#define IO_READ 1
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#define IO_WRITE 2
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#endif /* DIRECT_IO_ACCESS */
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#ifdef HAVE_PPDEV
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static int do_pp_port_access = -1; /* -1: uninitialized, 1: not available
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0: available);*/
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#endif
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#define BCD2BIN(a) \
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((a)%10 + ((a)>>4)%10*10 + ((a)>>8)%10*100 + ((a)>>12)%10*1000)
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#define BIN2BCD(a) \
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((a)%10 | (a)/10%10<<4 | (a)/100%10<<8 | (a)/1000%10<<12)
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static void set_timer(unsigned timer)
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{
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DWORD val = tmr_8253[timer].countmax;
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if (tmr_8253[timer].ctrlbyte_ch & 0x01)
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val = BCD2BIN(val);
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tmr_8253[timer].flags &= ~TMR_UPDATE;
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if (!QueryPerformanceCounter((LARGE_INTEGER*)&tmr_8253[timer].start_time))
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WARN("QueryPerformanceCounter should not fail!\n");
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switch (timer) {
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case 0: /* System timer counter divisor */
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DOSVM_SetTimer(val);
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break;
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case 1: /* RAM refresh */
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FIXME("RAM refresh counter handling not implemented !\n");
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break;
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case 2: /* cassette & speaker */
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/* speaker on ? */
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if ((parport_8255[1] & 3) == 3)
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{
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TRACE("Beep (freq: %d) !\n", 1193180 / val);
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Beep(1193180 / val, 20);
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}
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break;
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}
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}
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static WORD get_timer_val(unsigned timer)
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{
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LARGE_INTEGER time;
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WORD maxval, val = tmr_8253[timer].countmax;
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BYTE mode = tmr_8253[timer].ctrlbyte_ch >> 1 & 0x07;
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/* This is not strictly correct. In most cases the old countdown should
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* finish normally (by counting down to 0) or halt and not jump to 0.
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* But we are calculating and not counting, so this seems to be a good
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* solution and should work well with most (all?) programs
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*/
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if (tmr_8253[timer].flags & TMR_UPDATE)
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return 0;
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if (!QueryPerformanceCounter(&time))
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WARN("QueryPerformanceCounter should not fail!\n");
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time.QuadPart -= tmr_8253[timer].start_time;
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if (tmr_8253[timer].ctrlbyte_ch & 0x01)
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val = BCD2BIN(val);
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switch ( mode )
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{
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case 0:
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case 1:
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case 4:
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case 5:
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maxval = tmr_8253[timer].ctrlbyte_ch & 0x01 ? 9999 : 0xFFFF;
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break;
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case 2:
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case 3:
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maxval = val;
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break;
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default:
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ERR("Invalid PIT mode: %d\n", mode);
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return 0;
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}
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val = (val - time.QuadPart) % (maxval + 1);
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if (tmr_8253[timer].ctrlbyte_ch & 0x01)
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val = BIN2BCD(val);
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return val;
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}
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/**********************************************************************
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* IO_port_init
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*/
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/* set_IO_permissions(int val1, int val)
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* Helper function for IO_port_init
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*/
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#ifdef DIRECT_IO_ACCESS
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static void set_IO_permissions(int val1, int val, char rw)
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{
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int j;
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if (val1 != -1) {
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if (val == -1) val = 0x3ff;
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for (j = val1; j <= val; j++)
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port_permissions[j] |= rw;
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do_direct_port_access = 1;
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val1 = -1;
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} else if (val != -1) {
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do_direct_port_access = 1;
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port_permissions[val] |= rw;
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}
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}
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/* do_IO_port_init_read_or_write(char* temp, char rw)
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* Helper function for IO_port_init
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*/
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static void do_IO_port_init_read_or_write(const WCHAR *str, char rw)
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{
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int val, val1;
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unsigned int i;
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WCHAR *end;
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static const WCHAR allW[] = {'a','l','l',0};
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if (!strcmpiW(str, allW))
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{
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for (i=0; i < sizeof(port_permissions); i++)
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port_permissions[i] |= rw;
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}
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else
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{
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val = -1;
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val1 = -1;
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while (*str)
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{
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switch(*str)
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{
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case ',':
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case ' ':
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case '\t':
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set_IO_permissions(val1, val, rw);
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val1 = -1;
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val = -1;
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str++;
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break;
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case '-':
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val1 = val;
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if (val1 == -1) val1 = 0;
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str++;
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break;
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default:
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if (isdigitW(*str))
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{
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val = strtoulW( str, &end, 0 );
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if (end == str)
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{
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val = -1;
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str++;
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}
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else str = end;
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}
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break;
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}
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}
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set_IO_permissions(val1, val, rw);
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}
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}
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static inline BYTE inb( WORD port )
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{
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BYTE b;
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__asm__ __volatile__( "inb %w1,%0" : "=a" (b) : "d" (port) );
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return b;
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}
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static inline WORD inw( WORD port )
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{
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WORD w;
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__asm__ __volatile__( "inw %w1,%0" : "=a" (w) : "d" (port) );
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return w;
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}
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static inline DWORD inl( WORD port )
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{
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DWORD dw;
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__asm__ __volatile__( "inl %w1,%0" : "=a" (dw) : "d" (port) );
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return dw;
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}
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static inline void outb( BYTE value, WORD port )
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{
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__asm__ __volatile__( "outb %b0,%w1" : : "a" (value), "d" (port) );
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}
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static inline void outw( WORD value, WORD port )
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{
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__asm__ __volatile__( "outw %w0,%w1" : : "a" (value), "d" (port) );
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}
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static inline void outl( DWORD value, WORD port )
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{
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__asm__ __volatile__( "outl %0,%w1" : : "a" (value), "d" (port) );
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}
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static void IO_port_init(void)
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{
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char tmp[1024];
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HANDLE root, hkey;
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DWORD dummy;
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OBJECT_ATTRIBUTES attr;
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UNICODE_STRING nameW;
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static const WCHAR portsW[] = {'S','o','f','t','w','a','r','e','\\',
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'W','i','n','e','\\','V','D','M','\\','P','o','r','t','s',0};
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static const WCHAR readW[] = {'r','e','a','d',0};
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static const WCHAR writeW[] = {'w','r','i','t','e',0};
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do_direct_port_access = 0;
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/* Can we do that? */
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if (!iopl(3))
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{
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iopl(0);
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RtlOpenCurrentUser( KEY_ALL_ACCESS, &root );
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attr.Length = sizeof(attr);
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attr.RootDirectory = root;
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attr.ObjectName = &nameW;
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attr.Attributes = 0;
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attr.SecurityDescriptor = NULL;
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attr.SecurityQualityOfService = NULL;
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RtlInitUnicodeString( &nameW, portsW );
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/* @@ Wine registry key: HKCU\Software\Wine\VDM\Ports */
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if (!NtOpenKey( &hkey, KEY_ALL_ACCESS, &attr ))
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{
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RtlInitUnicodeString( &nameW, readW );
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if (!NtQueryValueKey( hkey, &nameW, KeyValuePartialInformation, tmp, sizeof(tmp), &dummy ))
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{
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WCHAR *str = (WCHAR *)((KEY_VALUE_PARTIAL_INFORMATION *)tmp)->Data;
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do_IO_port_init_read_or_write(str, IO_READ);
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}
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RtlInitUnicodeString( &nameW, writeW );
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if (!NtQueryValueKey( hkey, &nameW, KeyValuePartialInformation, tmp, sizeof(tmp), &dummy ))
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{
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WCHAR *str = (WCHAR *)((KEY_VALUE_PARTIAL_INFORMATION *)tmp)->Data;
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do_IO_port_init_read_or_write(str, IO_WRITE);
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}
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NtClose( hkey );
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}
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NtClose( root );
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}
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}
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|
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#endif /* DIRECT_IO_ACCESS */
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|
|
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#ifdef HAVE_PPDEV
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typedef struct _PPDEVICESTRUCT{
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int fd; /* NULL if device not available */
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char *devicename;
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int userbase; /* where wine thinks the ports are */
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DWORD lastaccess; /* or NULL if release */
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int timeout; /* time in second of inactivity to release the port */
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} PPDeviceStruct;
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static PPDeviceStruct PPDeviceList[5];
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static int PPDeviceNum=0;
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|
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static int IO_pp_sort(const void *p1,const void *p2)
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{
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return ((const PPDeviceStruct*)p1)->userbase - ((const PPDeviceStruct*)p2)->userbase;
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}
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|
|
/* IO_pp_init
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*
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* Read the ppdev entries from registry, open the device and check
|
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* for necessary IOCTRL
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* Report verbose about possible errors
|
|
*/
|
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static char IO_pp_init(void)
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{
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char name[80];
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char buffer[256];
|
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HANDLE root, hkey;
|
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int i,idx=0,fd,res,userbase,nports=0;
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char * timeout;
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|
char ret=1;
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int lasterror;
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OBJECT_ATTRIBUTES attr;
|
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UNICODE_STRING nameW;
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|
|
|
static const WCHAR configW[] = {'S','o','f','t','w','a','r','e','\\',
|
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'W','i','n','e','\\','V','D','M','\\','p','p','d','e','v',0};
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|
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TRACE("\n");
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|
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RtlOpenCurrentUser( KEY_ALL_ACCESS, &root );
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attr.Length = sizeof(attr);
|
|
attr.RootDirectory = root;
|
|
attr.ObjectName = &nameW;
|
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attr.Attributes = 0;
|
|
attr.SecurityDescriptor = NULL;
|
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attr.SecurityQualityOfService = NULL;
|
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RtlInitUnicodeString( &nameW, configW );
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|
|
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/* @@ Wine registry key: HKCU\Software\Wine\VDM\ppdev */
|
|
if (NtOpenKey( &hkey, KEY_ALL_ACCESS, &attr )) hkey = 0;
|
|
NtClose( root );
|
|
if (!hkey) return 1;
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|
|
for (;;)
|
|
{
|
|
DWORD total_size, len;
|
|
char temp[256];
|
|
KEY_VALUE_FULL_INFORMATION *info = (KEY_VALUE_FULL_INFORMATION *)temp;
|
|
|
|
if (NtEnumerateValueKey( hkey, idx, KeyValueFullInformation,
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temp, sizeof(temp), &total_size )) break;
|
|
if (info->Type != REG_SZ) break;
|
|
|
|
RtlUnicodeToMultiByteN( name, sizeof(name)-1, &len, info->Name, info->NameLength );
|
|
name[len] = 0;
|
|
RtlUnicodeToMultiByteN( buffer, sizeof(buffer)-1, &len,
|
|
(WCHAR *)(temp + info->DataOffset), total_size-info->DataOffset );
|
|
buffer[len] = 0;
|
|
|
|
idx++;
|
|
if(nports >4)
|
|
{
|
|
FIXME("Make the PPDeviceList larger than 5 elements\n");
|
|
break;
|
|
}
|
|
TRACE("Device '%s' at virtual userbase '%s'\n", buffer,name);
|
|
timeout = strchr(buffer,',');
|
|
if (timeout)
|
|
*timeout++=0;
|
|
fd=open(buffer,O_RDWR);
|
|
lasterror=errno;
|
|
if (fd == -1)
|
|
{
|
|
WARN("Configuration: No access to %s Cause: %s\n",buffer,strerror(lasterror));
|
|
WARN("Rejecting configuration item\n");
|
|
if (lasterror == ENODEV)
|
|
ERR("Is the ppdev module loaded?\n");
|
|
continue;
|
|
}
|
|
userbase = strtol(name, NULL, 16);
|
|
if ( errno == ERANGE)
|
|
{
|
|
WARN("Configuration: Invalid base %s for %s\n",name,buffer);
|
|
WARN("Rejecting configuration item\n");
|
|
continue;
|
|
}
|
|
if (ioctl (fd,PPCLAIM,0))
|
|
{
|
|
ERR("PPCLAIM rejected %s\n",buffer);
|
|
ERR("Perhaps the device is already in use or nonexistent\n");
|
|
continue;
|
|
}
|
|
if (nports > 0)
|
|
{
|
|
for (i=0; i<= nports; i++)
|
|
{
|
|
if (PPDeviceList[i].userbase == userbase)
|
|
{
|
|
WARN("Configuration: %s uses the same virtual ports as %s\n",
|
|
buffer,PPDeviceList[0].devicename);
|
|
WARN("Configuration: Rejecting configuration item\n");
|
|
userbase = 0;
|
|
break;
|
|
}
|
|
}
|
|
if (!userbase) continue;
|
|
}
|
|
/* Check for the minimum required IOCTLS */
|
|
if ((ioctl(fd,PPRDATA,&res))||
|
|
(ioctl(fd,PPRSTATUS,&res))||
|
|
(ioctl(fd,PPRCONTROL,&res)))
|
|
{
|
|
ERR("PPUSER IOCTL not available for parport device %s\n",buffer);
|
|
continue;
|
|
}
|
|
if (ioctl (fd,PPRELEASE,0))
|
|
{
|
|
ERR("PPRELEASE rejected %s\n",buffer);
|
|
ERR("Perhaps the device is already in use or nonexistent\n");
|
|
continue;
|
|
}
|
|
PPDeviceList[nports].devicename = HeapAlloc(GetProcessHeap(), 0, sizeof(buffer)+1);
|
|
if (!PPDeviceList[nports].devicename)
|
|
{
|
|
ERR("No (more) space for devicename\n");
|
|
break;
|
|
}
|
|
strcpy(PPDeviceList[nports].devicename,buffer);
|
|
PPDeviceList[nports].fd = fd;
|
|
PPDeviceList[nports].userbase = userbase;
|
|
PPDeviceList[nports].lastaccess=GetTickCount();
|
|
if (timeout)
|
|
{
|
|
PPDeviceList[nports].timeout = strtol(timeout, NULL, 10);
|
|
if (errno == ERANGE)
|
|
{
|
|
WARN("Configuration: Invalid timeout %s in configuration for %s, Setting to 0\n",
|
|
timeout,buffer);
|
|
PPDeviceList[nports].timeout = 0;
|
|
}
|
|
}
|
|
else
|
|
PPDeviceList[nports].timeout = 0;
|
|
nports++;
|
|
}
|
|
TRACE("found %d ports\n",nports);
|
|
NtClose( hkey );
|
|
|
|
PPDeviceNum= nports;
|
|
if (nports > 1)
|
|
/* sort in ascending order for userbase for faster access */
|
|
qsort (PPDeviceList,PPDeviceNum,sizeof(PPDeviceStruct),IO_pp_sort);
|
|
|
|
if (nports)
|
|
ret=0;
|
|
for (idx= 0;idx<PPDeviceNum; idx++)
|
|
TRACE("found device %s userbase %x fd %x timeout %d\n",
|
|
PPDeviceList[idx].devicename, PPDeviceList[idx].userbase,
|
|
PPDeviceList[idx].fd,PPDeviceList[idx].timeout);
|
|
/* FIXME:
|
|
register a timer callback perhaps every 30 seconds to release unused ports
|
|
Set lastaccess = 0 as indicator when port was released
|
|
*/
|
|
return ret;
|
|
}
|
|
|
|
/* IO_pp_do_access
|
|
*
|
|
* Do the actual IOCTL
|
|
* Return NULL on success
|
|
*/
|
|
static int IO_pp_do_access(int idx,int ppctl, DWORD* res)
|
|
{
|
|
int ret;
|
|
if (ioctl(PPDeviceList[idx].fd,PPCLAIM,0))
|
|
{
|
|
ERR("Can't reclaim device %s, PPUSER/PPDEV handling confused\n",
|
|
PPDeviceList[idx].devicename);
|
|
return 1;
|
|
}
|
|
ret = ioctl(PPDeviceList[idx].fd,ppctl,res);
|
|
if (ioctl(PPDeviceList[idx].fd,PPRELEASE,0))
|
|
{
|
|
ERR("Can't release device %s, PPUSER/PPDEV handling confused\n",
|
|
PPDeviceList[idx].devicename);
|
|
return 1;
|
|
}
|
|
return ret;
|
|
|
|
}
|
|
|
|
/* IO_pp_inp
|
|
*
|
|
* Check if we can satisfy the INP command with some of the configured PPDEV device
|
|
* Return NULL on success
|
|
*/
|
|
static int IO_pp_inp(int port, DWORD* res)
|
|
{
|
|
int idx,j=0;
|
|
|
|
for (idx=0;idx<PPDeviceNum ;idx++)
|
|
{
|
|
j = port - PPDeviceList[idx].userbase;
|
|
if (j <0) return 1;
|
|
switch (j)
|
|
{
|
|
case 0:
|
|
return IO_pp_do_access(idx,PPRDATA,res);
|
|
case 1:
|
|
return IO_pp_do_access(idx,PPRSTATUS,res);
|
|
case 2:
|
|
return IO_pp_do_access(idx,PPRCONTROL,res);
|
|
case 0x400:
|
|
case 0x402:
|
|
case 3:
|
|
case 4:
|
|
case 0x401:
|
|
FIXME("Port 0x%x not accessible for reading with ppdev\n",port);
|
|
FIXME("If this is causing problems, try direct port access\n");
|
|
return 1;
|
|
default:
|
|
break;
|
|
}
|
|
}
|
|
return 1;
|
|
}
|
|
|
|
/* IO_pp_outp
|
|
*
|
|
* Check if we can satisfy the OUTP command with some of the configured PPDEV device
|
|
* Return NULL on success
|
|
*/
|
|
static BOOL IO_pp_outp(int port, DWORD* res)
|
|
{
|
|
int idx,j=0;
|
|
|
|
for (idx=0;idx<PPDeviceNum ;idx++)
|
|
{
|
|
j = port - PPDeviceList[idx].userbase;
|
|
if (j <0) return 1;
|
|
switch (j)
|
|
{
|
|
case 0:
|
|
return IO_pp_do_access(idx,PPWDATA,res);
|
|
case 2:
|
|
{
|
|
/* We can't switch port direction via PPWCONTROL,
|
|
so do it via PPDATADIR
|
|
*/
|
|
DWORD mode = *res & 0x20;
|
|
IO_pp_do_access(idx,PPDATADIR,&mode);
|
|
mode = (*res & ~0x20);
|
|
return IO_pp_do_access(idx,PPWCONTROL,&mode);
|
|
}
|
|
|
|
case 1:
|
|
case 0x400:
|
|
case 0x402:
|
|
case 3:
|
|
case 4:
|
|
case 0x401:
|
|
FIXME("Port %d not accessible for writing with ppdev\n",port);
|
|
FIXME("If this is causing problems, try direct port access\n");
|
|
return 1;
|
|
default:
|
|
break;
|
|
}
|
|
}
|
|
return TRUE;
|
|
}
|
|
|
|
#endif /* HAVE_PPDEV */
|
|
|
|
|
|
/**********************************************************************
|
|
* DOSVM_inport
|
|
*
|
|
* Note: The size argument has to be handled correctly _externally_
|
|
* (as we always return a DWORD)
|
|
*/
|
|
DWORD DOSVM_inport( int port, int size )
|
|
{
|
|
DWORD res = ~0U;
|
|
|
|
TRACE("%d-byte value from port 0x%04x\n", size, port );
|
|
|
|
DOSMEM_InitDosMemory();
|
|
|
|
#ifdef HAVE_PPDEV
|
|
if (do_pp_port_access == -1) do_pp_port_access =IO_pp_init();
|
|
if ((do_pp_port_access == 0 ) && (size == 1))
|
|
{
|
|
if (!IO_pp_inp(port,&res)) return res;
|
|
}
|
|
#endif
|
|
|
|
#ifdef DIRECT_IO_ACCESS
|
|
if (do_direct_port_access == -1) IO_port_init();
|
|
if ((do_direct_port_access)
|
|
/* Make sure we have access to the port */
|
|
&& (port_permissions[port] & IO_READ))
|
|
{
|
|
iopl(3);
|
|
switch(size)
|
|
{
|
|
case 1: res = inb( port ); break;
|
|
case 2: res = inw( port ); break;
|
|
case 4: res = inl( port ); break;
|
|
}
|
|
iopl(0);
|
|
return res;
|
|
}
|
|
#endif
|
|
|
|
switch (port)
|
|
{
|
|
case 0x40:
|
|
case 0x41:
|
|
case 0x42:
|
|
{
|
|
BYTE chan = port & 3;
|
|
WORD tempval = tmr_8253[chan].flags & TMR_LATCHED
|
|
? tmr_8253[chan].latch : get_timer_val(chan);
|
|
|
|
if (tmr_8253[chan].flags & TMR_STATUS)
|
|
{
|
|
WARN("Read-back status\n");
|
|
/* We differ slightly from the spec:
|
|
* - TMR_UPDATE is already set with the first write
|
|
* of a two byte counter update
|
|
* - 0x80 should be set if OUT signal is 1 (high)
|
|
*/
|
|
tmr_8253[chan].flags &= ~TMR_STATUS;
|
|
res = (tmr_8253[chan].ctrlbyte_ch & 0x3F) |
|
|
(tmr_8253[chan].flags & TMR_UPDATE ? 0x40 : 0x00);
|
|
break;
|
|
}
|
|
switch ((tmr_8253[chan].ctrlbyte_ch & 0x30) >> 4)
|
|
{
|
|
case 0:
|
|
res = 0; /* shouldn't happen? */
|
|
break;
|
|
case 1: /* read lo byte */
|
|
res = (BYTE)tempval;
|
|
tmr_8253[chan].flags &= ~TMR_LATCHED;
|
|
break;
|
|
case 3: /* read lo byte, then hi byte */
|
|
tmr_8253[chan].flags ^= TMR_RTOGGLE; /* toggle */
|
|
if (tmr_8253[chan].flags & TMR_RTOGGLE)
|
|
{
|
|
res = (BYTE)tempval;
|
|
break;
|
|
}
|
|
/* else [fall through if read hi byte !] */
|
|
case 2: /* read hi byte */
|
|
res = (BYTE)(tempval >> 8);
|
|
tmr_8253[chan].flags &= ~TMR_LATCHED;
|
|
break;
|
|
}
|
|
}
|
|
break;
|
|
case 0x60:
|
|
res = DOSVM_Int09ReadScan(NULL);
|
|
break;
|
|
case 0x61:
|
|
res = (DWORD)parport_8255[1];
|
|
break;
|
|
case 0x62:
|
|
res = (DWORD)parport_8255[2];
|
|
break;
|
|
case 0x70:
|
|
res = (DWORD)cmosaddress;
|
|
break;
|
|
case 0x71:
|
|
if (!cmos_image_initialized)
|
|
{
|
|
IO_FixCMOSCheckSum();
|
|
cmos_image_initialized = 1;
|
|
}
|
|
res = (DWORD)cmosimage[cmosaddress & 0x3f];
|
|
break;
|
|
case 0x200:
|
|
case 0x201:
|
|
res = ~0U; /* no joystick */
|
|
break;
|
|
case 0x22a:
|
|
case 0x22c:
|
|
case 0x22e:
|
|
res = (DWORD)SB_ioport_in( port );
|
|
break;
|
|
/* VGA read registers */
|
|
case 0x3b4: /* CRT Controller Register - Index (MDA) */
|
|
case 0x3b5: /* CRT Controller Register - Other (MDA) */
|
|
case 0x3ba: /* General Register - Input status 1 (MDA) */
|
|
case 0x3c0: /* Attribute Controller - Address */
|
|
case 0x3c1: /* Attribute Controller - Other */
|
|
case 0x3c2: /* General Register - Input status 0 */
|
|
case 0x3c3: /* General Register - Video subsystem enable */
|
|
case 0x3c4: /* Sequencer Register - Address */
|
|
case 0x3c5: /* Sequencer Register - Other */
|
|
case 0x3c6:
|
|
case 0x3c7: /* General Register - DAC State */
|
|
case 0x3c8:
|
|
case 0x3c9:
|
|
case 0x3ca: /* General Register - Feature control */
|
|
case 0x3cb:
|
|
case 0x3cc: /* General Register - Misc output */
|
|
case 0x3cd:
|
|
case 0x3ce: /* Graphics Controller Register - Address */
|
|
case 0x3cf: /* Graphics Controller Register - Other */
|
|
case 0x3d0:
|
|
case 0x3d1:
|
|
case 0x3d2:
|
|
case 0x3d3:
|
|
case 0x3d4: /* CRT Controller Register - Index (CGA) */
|
|
case 0x3d5: /* CRT Controller Register - Other (CGA) */
|
|
case 0x3d6:
|
|
case 0x3d7:
|
|
case 0x3d8:
|
|
case 0x3d9:
|
|
case 0x3da:
|
|
case 0x3db:
|
|
case 0x3dc:
|
|
case 0x3dd:
|
|
case 0x3de:
|
|
case 0x3df:
|
|
if (size > 1)
|
|
FIXME("Trying to read more than one byte from VGA!\n");
|
|
res = (DWORD)VGA_ioport_in( port );
|
|
break;
|
|
case 0x00:
|
|
case 0x01:
|
|
case 0x02:
|
|
case 0x03:
|
|
case 0x04:
|
|
case 0x05:
|
|
case 0x06:
|
|
case 0x07:
|
|
case 0xC0:
|
|
case 0xC2:
|
|
case 0xC4:
|
|
case 0xC6:
|
|
case 0xC8:
|
|
case 0xCA:
|
|
case 0xCC:
|
|
case 0xCE:
|
|
case 0x87:
|
|
case 0x83:
|
|
case 0x81:
|
|
case 0x82:
|
|
case 0x8B:
|
|
case 0x89:
|
|
case 0x8A:
|
|
case 0x487:
|
|
case 0x483:
|
|
case 0x481:
|
|
case 0x482:
|
|
case 0x48B:
|
|
case 0x489:
|
|
case 0x48A:
|
|
case 0x08:
|
|
case 0xD0:
|
|
case 0x0D:
|
|
case 0xDA:
|
|
res = (DWORD)DMA_ioport_in( port );
|
|
break;
|
|
default:
|
|
WARN("Direct I/O read attempted from port %x\n", port);
|
|
break;
|
|
}
|
|
return res;
|
|
}
|
|
|
|
|
|
/**********************************************************************
|
|
* DOSVM_outport
|
|
*/
|
|
void DOSVM_outport( int port, int size, DWORD value )
|
|
{
|
|
TRACE("IO: 0x%x (%d-byte value) to port 0x%04x\n", value, size, port );
|
|
|
|
DOSMEM_InitDosMemory();
|
|
|
|
#ifdef HAVE_PPDEV
|
|
if (do_pp_port_access == -1) do_pp_port_access = IO_pp_init();
|
|
if ((do_pp_port_access == 0) && (size == 1))
|
|
{
|
|
if (!IO_pp_outp(port,&value)) return;
|
|
}
|
|
#endif
|
|
|
|
#ifdef DIRECT_IO_ACCESS
|
|
|
|
if (do_direct_port_access == -1) IO_port_init();
|
|
if ((do_direct_port_access)
|
|
/* Make sure we have access to the port */
|
|
&& (port_permissions[port] & IO_WRITE))
|
|
{
|
|
iopl(3);
|
|
switch(size)
|
|
{
|
|
case 1: outb( LOBYTE(value), port ); break;
|
|
case 2: outw( LOWORD(value), port ); break;
|
|
case 4: outl( value, port ); break;
|
|
}
|
|
iopl(0);
|
|
return;
|
|
}
|
|
#endif
|
|
|
|
switch (port)
|
|
{
|
|
case 0x20:
|
|
DOSVM_PIC_ioport_out( port, (BYTE)value );
|
|
break;
|
|
case 0x40:
|
|
case 0x41:
|
|
case 0x42:
|
|
{
|
|
BYTE chan = port & 3;
|
|
|
|
tmr_8253[chan].flags |= TMR_UPDATE;
|
|
switch ((tmr_8253[chan].ctrlbyte_ch & 0x30) >> 4)
|
|
{
|
|
case 0:
|
|
break; /* shouldn't happen? */
|
|
case 1: /* write lo byte */
|
|
tmr_8253[chan].countmax =
|
|
(tmr_8253[chan].countmax & 0xff00) | (BYTE)value;
|
|
break;
|
|
case 3: /* write lo byte, then hi byte */
|
|
tmr_8253[chan].flags ^= TMR_WTOGGLE; /* toggle */
|
|
if (tmr_8253[chan].flags & TMR_WTOGGLE)
|
|
{
|
|
tmr_8253[chan].countmax =
|
|
(tmr_8253[chan].countmax & 0xff00) | (BYTE)value;
|
|
break;
|
|
}
|
|
/* else [fall through if write hi byte !] */
|
|
case 2: /* write hi byte */
|
|
tmr_8253[chan].countmax =
|
|
(tmr_8253[chan].countmax & 0x00ff) | ((BYTE)value << 8);
|
|
break;
|
|
}
|
|
/* if programming is finished, update to new value */
|
|
if ((tmr_8253[chan].ctrlbyte_ch & 0x30) &&
|
|
!(tmr_8253[chan].flags & TMR_WTOGGLE))
|
|
set_timer(chan);
|
|
}
|
|
break;
|
|
case 0x43:
|
|
{
|
|
BYTE chan = ((BYTE)value & 0xc0) >> 6;
|
|
/* ctrl byte for specific timer channel */
|
|
if (chan == 3)
|
|
{
|
|
if ( !(value & 0x20) )
|
|
{
|
|
if ((value & 0x02) && !(tmr_8253[0].flags & TMR_LATCHED))
|
|
{
|
|
tmr_8253[0].flags |= TMR_LATCHED;
|
|
tmr_8253[0].latch = get_timer_val(0);
|
|
}
|
|
if ((value & 0x04) && !(tmr_8253[1].flags & TMR_LATCHED))
|
|
{
|
|
tmr_8253[1].flags |= TMR_LATCHED;
|
|
tmr_8253[1].latch = get_timer_val(1);
|
|
}
|
|
if ((value & 0x08) && !(tmr_8253[2].flags & TMR_LATCHED))
|
|
{
|
|
tmr_8253[2].flags |= TMR_LATCHED;
|
|
tmr_8253[2].latch = get_timer_val(2);
|
|
}
|
|
}
|
|
|
|
if ( !(value & 0x10) )
|
|
{
|
|
if (value & 0x02)
|
|
tmr_8253[0].flags |= TMR_STATUS;
|
|
if (value & 0x04)
|
|
tmr_8253[1].flags |= TMR_STATUS;
|
|
if (value & 0x08)
|
|
tmr_8253[2].flags |= TMR_STATUS;
|
|
}
|
|
break;
|
|
}
|
|
switch (((BYTE)value & 0x30) >> 4)
|
|
{
|
|
case 0: /* latch timer */
|
|
if ( !(tmr_8253[chan].flags & TMR_LATCHED) )
|
|
{
|
|
tmr_8253[chan].flags |= TMR_LATCHED;
|
|
tmr_8253[chan].latch = get_timer_val(chan);
|
|
}
|
|
break;
|
|
case 1: /* write lo byte only */
|
|
case 2: /* write hi byte only */
|
|
case 3: /* write lo byte, then hi byte */
|
|
tmr_8253[chan].ctrlbyte_ch = (BYTE)value;
|
|
tmr_8253[chan].countmax = 0;
|
|
tmr_8253[chan].flags = TMR_UPDATE;
|
|
break;
|
|
}
|
|
}
|
|
break;
|
|
case 0x61:
|
|
parport_8255[1] = (BYTE)value;
|
|
if (((parport_8255[1] & 3) == 3) && (tmr_8253[2].countmax != 1))
|
|
{
|
|
TRACE("Beep (freq: %d) !\n", 1193180 / tmr_8253[2].countmax);
|
|
Beep(1193180 / tmr_8253[2].countmax, 20);
|
|
}
|
|
break;
|
|
case 0x70:
|
|
cmosaddress = (BYTE)value & 0x7f;
|
|
break;
|
|
case 0x71:
|
|
if (!cmos_image_initialized)
|
|
{
|
|
IO_FixCMOSCheckSum();
|
|
cmos_image_initialized = 1;
|
|
}
|
|
cmosimage[cmosaddress & 0x3f] = (BYTE)value;
|
|
break;
|
|
case 0x226:
|
|
case 0x22c:
|
|
SB_ioport_out( port, (BYTE)value );
|
|
break;
|
|
/* VGA Write registers */
|
|
case 0x3b4: /* CRT Controller Register - Index (MDA) */
|
|
case 0x3b5: /* CRT Controller Register - Other (MDA) */
|
|
case 0x3ba: /* General Register - Feature Control */
|
|
case 0x3c0: /* Attribute Controller - Address/Other */
|
|
case 0x3c1:
|
|
case 0x3c2: /* General Register - Misc output */
|
|
case 0x3c3: /* General Register - Video subsystem enable */
|
|
case 0x3c4: /* Sequencer Register - Address */
|
|
case 0x3c5: /* Sequencer Register - Other */
|
|
case 0x3c6:
|
|
case 0x3c7:
|
|
case 0x3c8:
|
|
case 0x3c9:
|
|
case 0x3ca:
|
|
case 0x3cb:
|
|
case 0x3cc:
|
|
case 0x3cd:
|
|
case 0x3ce: /* Graphics Controller Register - Address */
|
|
case 0x3cf: /* Graphics Controller Register - Other */
|
|
case 0x3d0:
|
|
case 0x3d1:
|
|
case 0x3d2:
|
|
case 0x3d3:
|
|
case 0x3d4: /* CRT Controller Register - Index (CGA) */
|
|
case 0x3d5: /* CRT Controller Register - Other (CGA) */
|
|
case 0x3d6:
|
|
case 0x3d7:
|
|
case 0x3d8:
|
|
case 0x3d9:
|
|
case 0x3da:
|
|
case 0x3db:
|
|
case 0x3dc:
|
|
case 0x3dd:
|
|
case 0x3de:
|
|
case 0x3df:
|
|
VGA_ioport_out( port, LOBYTE(value) );
|
|
if(size > 1) {
|
|
VGA_ioport_out( port+1, HIBYTE(value) );
|
|
if(size > 2) {
|
|
VGA_ioport_out( port+2, LOBYTE(HIWORD(value)) );
|
|
VGA_ioport_out( port+3, HIBYTE(HIWORD(value)) );
|
|
}
|
|
}
|
|
break;
|
|
case 0x00:
|
|
case 0x01:
|
|
case 0x02:
|
|
case 0x03:
|
|
case 0x04:
|
|
case 0x05:
|
|
case 0x06:
|
|
case 0x07:
|
|
case 0xC0:
|
|
case 0xC2:
|
|
case 0xC4:
|
|
case 0xC6:
|
|
case 0xC8:
|
|
case 0xCA:
|
|
case 0xCC:
|
|
case 0xCE:
|
|
case 0x87:
|
|
case 0x83:
|
|
case 0x81:
|
|
case 0x82:
|
|
case 0x8B:
|
|
case 0x89:
|
|
case 0x8A:
|
|
case 0x487:
|
|
case 0x483:
|
|
case 0x481:
|
|
case 0x482:
|
|
case 0x48B:
|
|
case 0x489:
|
|
case 0x48A:
|
|
case 0x08:
|
|
case 0xD0:
|
|
case 0x0B:
|
|
case 0xD6:
|
|
case 0x0A:
|
|
case 0xD4:
|
|
case 0x0F:
|
|
case 0xDE:
|
|
case 0x09:
|
|
case 0xD2:
|
|
case 0x0C:
|
|
case 0xD8:
|
|
case 0x0D:
|
|
case 0xDA:
|
|
case 0x0E:
|
|
case 0xDC:
|
|
DMA_ioport_out( port, (BYTE)value );
|
|
break;
|
|
default:
|
|
WARN("Direct I/O write attempted to port %x\n", port );
|
|
break;
|
|
}
|
|
}
|