637 lines
19 KiB
C
637 lines
19 KiB
C
/*
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* Emulation of priviledged instructions
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*
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* Copyright 1995 Alexandre Julliard
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*/
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#include <stdio.h>
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#include "windows.h"
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#include "ldt.h"
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#include "miscemu.h"
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#include "registers.h"
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#define STACK_reg(context) \
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((GET_SEL_FLAGS(SS_reg(context)) & LDT_FLAGS_32BIT) ? \
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ESP_reg(context) : SP_reg(context))
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#define STACK_PTR(context) \
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(PTR_SEG_OFF_TO_LIN(SS_reg(context),STACK_reg(context)))
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/***********************************************************************
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* INSTR_ReplaceSelector
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*
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* Try to replace an invalid selector by a valid one.
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* For now, only selector 0x40 is handled here.
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*/
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static WORD INSTR_ReplaceSelector( struct sigcontext_struct *context, WORD sel)
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{
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if (sel == 0x40)
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{
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fprintf( stderr, "Direct access to segment 0x40 (cs:ip=%04x:%04lx).\n",
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CS_reg(context), EIP_reg(context) );
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DOSMEM_Alarm(); /* Increment BIOS clock */
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return DOSMEM_BiosSeg;
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}
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return 0; /* Can't replace selector */
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}
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/***********************************************************************
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* INSTR_GetOperandAddr
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*
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* Return the address of an instruction operand (from the mod/rm byte).
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*/
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static BYTE *INSTR_GetOperandAddr( struct sigcontext_struct *context,
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BYTE *instr, int long_addr,
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int segprefix, int *len )
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{
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int mod, rm, base, index = 0, ss = 0, seg = 0, off;
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#define GET_VAL(val,type) \
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{ *val = *(type *)instr; instr += sizeof(type); *len += sizeof(type); }
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*len = 0;
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GET_VAL( &mod, BYTE );
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rm = mod & 7;
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mod >>= 6;
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if (mod == 3)
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{
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switch(rm)
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{
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case 0: return (BYTE *)&EAX_reg(context);
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case 1: return (BYTE *)&ECX_reg(context);
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case 2: return (BYTE *)&EDX_reg(context);
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case 3: return (BYTE *)&EBX_reg(context);
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case 4: return (BYTE *)&ESP_reg(context);
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case 5: return (BYTE *)&EBP_reg(context);
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case 6: return (BYTE *)&ESI_reg(context);
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case 7: return (BYTE *)&EDI_reg(context);
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}
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}
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if (long_addr)
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{
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if (rm == 4)
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{
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BYTE sib;
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GET_VAL( &sib, BYTE );
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rm = sib & 7;
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ss = sib >> 6;
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switch(sib >> 3)
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{
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case 0: index = EAX_reg(context); break;
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case 1: index = ECX_reg(context); break;
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case 2: index = EDX_reg(context); break;
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case 3: index = EBX_reg(context); break;
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case 4: index = 0; break;
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case 5: index = EBP_reg(context); break;
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case 6: index = ESI_reg(context); break;
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case 7: index = EDI_reg(context); break;
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}
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}
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switch(rm)
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{
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case 0: base = EAX_reg(context); seg = DS_reg(context); break;
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case 1: base = ECX_reg(context); seg = DS_reg(context); break;
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case 2: base = EDX_reg(context); seg = DS_reg(context); break;
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case 3: base = EBX_reg(context); seg = DS_reg(context); break;
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case 4: base = ESP_reg(context); seg = SS_reg(context); break;
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case 5: base = EBP_reg(context); seg = SS_reg(context); break;
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case 6: base = ESI_reg(context); seg = DS_reg(context); break;
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case 7: base = EDI_reg(context); seg = DS_reg(context); break;
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}
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switch (mod)
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{
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case 0:
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if (rm == 5) /* special case: ds:(disp32) */
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{
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GET_VAL( &base, DWORD );
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seg = DS_reg(context);
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}
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break;
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case 1: /* 8-bit disp */
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GET_VAL( &off, BYTE );
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base += (signed char)off;
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break;
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case 2: /* 32-bit disp */
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GET_VAL( &off, DWORD );
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base += (signed long)off;
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break;
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}
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}
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else /* short address */
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{
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switch(rm)
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{
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case 0: /* ds:(bx,si) */
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base = BX_reg(context) + SI_reg(context);
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seg = DS_reg(context);
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break;
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case 1: /* ds:(bx,di) */
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base = BX_reg(context) + DI_reg(context);
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seg = DS_reg(context);
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break;
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case 2: /* ss:(bp,si) */
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base = BP_reg(context) + SI_reg(context);
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seg = SS_reg(context);
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break;
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case 3: /* ss:(bp,di) */
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base = BP_reg(context) + DI_reg(context);
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seg = SS_reg(context);
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break;
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case 4: /* ds:(si) */
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base = SI_reg(context);
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seg = DS_reg(context);
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break;
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case 5: /* ds:(di) */
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base = DI_reg(context);
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seg = DS_reg(context);
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break;
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case 6: /* ss:(bp) */
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base = BP_reg(context);
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seg = SS_reg(context);
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break;
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case 7: /* ds:(bx) */
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base = BX_reg(context);
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seg = DS_reg(context);
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break;
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}
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switch(mod)
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{
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case 0:
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if (rm == 6) /* special case: ds:(disp16) */
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{
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GET_VAL( &base, WORD );
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seg = DS_reg(context);
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}
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break;
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case 1: /* 8-bit disp */
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GET_VAL( &off, BYTE );
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base += (signed char)off;
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break;
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case 2: /* 16-bit disp */
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GET_VAL( &off, WORD );
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base += (signed short)off;
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break;
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}
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base &= 0xffff;
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}
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if (segprefix != -1) seg = segprefix;
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/* FIXME: should check limit of the segment here */
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return (BYTE *)PTR_SEG_OFF_TO_LIN( seg, (base + (index << ss)) );
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}
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/***********************************************************************
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* INSTR_EmulateLDS
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*
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* Emulate the LDS (and LES,LFS,etc.) instruction.
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*/
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static BOOL INSTR_EmulateLDS( struct sigcontext_struct *context,
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BYTE *instr, int long_op, int long_addr,
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int segprefix, int *len )
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{
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BYTE *regmodrm = instr + 1 + (*instr == 0x0f);
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BYTE *addr = INSTR_GetOperandAddr( context, regmodrm,
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long_addr, segprefix, len );
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WORD seg = *(WORD *)(addr + (long_op ? 4 : 2));
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if (!(seg = INSTR_ReplaceSelector( context, seg )))
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return FALSE; /* Unable to emulate it */
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/* Now store the offset in the correct register */
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switch((*regmodrm >> 3) & 7)
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{
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case 0:
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if (long_op) EAX_reg(context) = *(DWORD *)addr;
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else AX_reg(context) = *(WORD *)addr;
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break;
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case 1:
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if (long_op) ECX_reg(context) = *(DWORD *)addr;
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else CX_reg(context) = *(WORD *)addr;
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break;
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case 2:
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if (long_op) EDX_reg(context) = *(DWORD *)addr;
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else DX_reg(context) = *(WORD *)addr;
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break;
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case 3:
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if (long_op) EBX_reg(context) = *(DWORD *)addr;
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else BX_reg(context) = *(WORD *)addr;
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break;
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case 4:
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if (long_op) ESP_reg(context) = *(DWORD *)addr;
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else SP_reg(context) = *(WORD *)addr;
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break;
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case 5:
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if (long_op) EBP_reg(context) = *(DWORD *)addr;
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else BP_reg(context) = *(WORD *)addr;
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break;
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case 6:
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if (long_op) ESI_reg(context) = *(DWORD *)addr;
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else SI_reg(context) = *(WORD *)addr;
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break;
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case 7:
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if (long_op) EDI_reg(context) = *(DWORD *)addr;
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else DI_reg(context) = *(WORD *)addr;
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break;
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}
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/* Store the correct segment in the segment register */
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switch(*instr)
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{
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case 0xc4: ES_reg(context) = seg; break; /* les */
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case 0xc5: DS_reg(context) = seg; break; /* lds */
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case 0x0f: switch(instr[1])
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{
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case 0xb2: SS_reg(context) = seg; break; /* lss */
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#ifdef FS_reg
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case 0xb4: FS_reg(context) = seg; break; /* lfs */
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#endif
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#ifdef GS_reg
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case 0xb5: GS_reg(context) = seg; break; /* lgs */
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#endif
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}
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break;
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}
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/* Add the opcode size to the total length */
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*len += 1 + (*instr == 0x0f);
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return TRUE;
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}
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/***********************************************************************
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* INSTR_EmulateInstruction
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*
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* Emulate a priviledged instruction. Returns TRUE if emulation successful.
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*/
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BOOL INSTR_EmulateInstruction( struct sigcontext_struct *context )
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{
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int prefix, segprefix, prefixlen, len, repX, long_op, long_addr;
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BYTE *instr;
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long_op = long_addr = (GET_SEL_FLAGS(CS_reg(context)) & LDT_FLAGS_32BIT) != 0;
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instr = (BYTE *) PTR_SEG_OFF_TO_LIN( CS_reg(context), EIP_reg(context) );
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/* First handle any possible prefix */
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segprefix = -1; /* no prefix */
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prefix = 1;
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repX = 0;
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prefixlen = 0;
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while(prefix)
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{
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switch(*instr)
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{
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case 0x2e:
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segprefix = CS_reg(context);
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break;
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case 0x36:
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segprefix = SS_reg(context);
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break;
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case 0x3e:
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segprefix = DS_reg(context);
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break;
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case 0x26:
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segprefix = ES_reg(context);
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break;
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#ifdef FS_reg
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case 0x64:
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segprefix = FS_reg(context);
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break;
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#endif
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#ifdef GS_reg
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case 0x65:
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segprefix = GS_reg(context);
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break;
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#endif
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case 0x66:
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long_op = !long_op; /* opcode size prefix */
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break;
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case 0x67:
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long_addr = !long_addr; /* addr size prefix */
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break;
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case 0xf0: /* lock */
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break;
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case 0xf2: /* repne */
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repX = 1;
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break;
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case 0xf3: /* repe */
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repX = 2;
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break;
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default:
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prefix = 0; /* no more prefixes */
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break;
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}
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if (prefix)
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{
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instr++;
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prefixlen++;
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}
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}
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/* Now look at the actual instruction */
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switch(*instr)
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{
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case 0x07: /* pop es */
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case 0x17: /* pop ss */
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case 0x1f: /* pop ds */
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{
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WORD seg = *(WORD *)STACK_PTR( context );
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if ((seg = INSTR_ReplaceSelector( context, seg )) != 0)
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{
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switch(*instr)
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{
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case 0x07: ES_reg(context) = seg; break;
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case 0x17: SS_reg(context) = seg; break;
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case 0x1f: DS_reg(context) = seg; break;
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}
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STACK_reg(context) += long_op ? 4 : 2;
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EIP_reg(context) += prefixlen + 1;
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return TRUE;
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}
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}
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break; /* Unable to emulate it */
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case 0x0f: /* extended instruction */
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switch(instr[1])
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{
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#ifdef FS_reg
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case 0xa1: /* pop fs */
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{
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WORD seg = *(WORD *)STACK_PTR( context );
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if ((seg = INSTR_ReplaceSelector( context, seg )) != 0)
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{
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FS_reg(context) = seg;
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STACK_reg(context) += long_op ? 4 : 2;
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EIP_reg(context) += prefixlen + 2;
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return TRUE;
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}
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}
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break;
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#endif /* FS_reg */
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#ifdef GS_reg
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case 0xa9: /* pop gs */
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{
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WORD seg = *(WORD *)STACK_PTR( context );
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if ((seg = INSTR_ReplaceSelector( context, seg )) != 0)
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{
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GS_reg(context) = seg;
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STACK_reg(context) += long_op ? 4 : 2;
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EIP_reg(context) += prefixlen + 2;
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return TRUE;
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}
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}
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break;
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#endif /* GS_reg */
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case 0xb2: /* lss addr,reg */
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#ifdef FS_reg
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case 0xb4: /* lfs addr,reg */
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#endif
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#ifdef GS_reg
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case 0xb5: /* lgs addr,reg */
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#endif
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if (INSTR_EmulateLDS( context, instr, long_op,
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long_addr, segprefix, &len ))
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{
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EIP_reg(context) += prefixlen + len;
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return TRUE;
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}
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break;
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}
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break; /* Unable to emulate it */
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case 0x6c: /* insb */
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case 0x6d: /* insw/d */
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case 0x6e: /* outsb */
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case 0x6f: /* outsw/d */
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{
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int typ = *instr; /* Just in case it's overwritten. */
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int outp = (typ >= 0x6e);
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unsigned long count = repX ?
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(long_addr ? ECX_reg(context) : CX_reg(context)) : 1;
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int opsize = (typ & 1) ? (long_op ? 4 : 2) : 1;
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int step = (EFL_reg(context) & 0x400) ? -opsize : +opsize;
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int seg = outp ? DS_reg(context) : ES_reg(context); /* FIXME: is this right? */
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if (outp)
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/* FIXME: Check segment readable. */
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(void)0;
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else
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/* FIXME: Check segment writeable. */
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(void)0;
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if (repX)
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if (long_addr)
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ECX_reg(context) = 0;
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else
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CX_reg(context) = 0;
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while (count-- > 0)
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{
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void *data;
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if (outp)
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{
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data = PTR_SEG_OFF_TO_LIN (seg,
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long_addr ? ESI_reg(context) : SI_reg(context));
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if (long_addr) ESI_reg(context) += step;
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else SI_reg(context) += step;
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}
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else
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{
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data = PTR_SEG_OFF_TO_LIN (seg,
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long_addr ? EDI_reg(context) : DI_reg(context));
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if (long_addr) EDI_reg(context) += step;
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else DI_reg(context) += step;
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}
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switch (typ)
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{
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case 0x6c:
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*((BYTE *)data) = inport( DX_reg(context), 1);
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break;
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case 0x6d:
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if (long_op)
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*((DWORD *)data) = inport( DX_reg(context), 4);
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else
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*((WORD *)data) = inport( DX_reg(context), 2);
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break;
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case 0x6e:
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outport( DX_reg(context), 1, *((BYTE *)data));
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break;
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case 0x6f:
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if (long_op)
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outport( DX_reg(context), 4, *((DWORD *)data));
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else
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outport( DX_reg(context), 2, *((WORD *)data));
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break;
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}
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}
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EIP_reg(context) += prefixlen + 1;
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}
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return TRUE;
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case 0x8e: /* mov XX,segment_reg */
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{
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WORD seg = *(WORD *)INSTR_GetOperandAddr( context, instr + 1,
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long_addr, segprefix, &len );
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if (!(seg = INSTR_ReplaceSelector( context, seg )))
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break; /* Unable to emulate it */
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switch((instr[1] >> 3) & 7)
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{
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case 0:
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ES_reg(context) = seg;
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EIP_reg(context) += prefixlen + len + 1;
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return TRUE;
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case 1: /* cs */
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break;
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case 2:
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SS_reg(context) = seg;
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EIP_reg(context) += prefixlen + len + 1;
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return TRUE;
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case 3:
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DS_reg(context) = seg;
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EIP_reg(context) += prefixlen + len + 1;
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return TRUE;
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case 4:
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#ifdef FS_reg
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FS_reg(context) = seg;
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EIP_reg(context) += prefixlen + len + 1;
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return TRUE;
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#endif
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case 5:
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#ifdef GS_reg
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GS_reg(context) = seg;
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EIP_reg(context) += prefixlen + len + 1;
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return TRUE;
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#endif
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case 6: /* unused */
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case 7: /* unused */
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break;
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}
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}
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break; /* Unable to emulate it */
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case 0xc4: /* les addr,reg */
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case 0xc5: /* lds addr,reg */
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if (INSTR_EmulateLDS( context, instr, long_op,
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long_addr, segprefix, &len ))
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{
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EIP_reg(context) += prefixlen + len;
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return TRUE;
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}
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break; /* Unable to emulate it */
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case 0xcd: /* int <XX> */
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if (long_op)
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|
{
|
|
fprintf(stderr, "int xx from 32-bit code is not supported.\n");
|
|
break; /* Unable to emulate it */
|
|
}
|
|
else
|
|
{
|
|
SEGPTR addr = INT_GetHandler( instr[1] );
|
|
WORD *stack = (WORD *)STACK_PTR( context );
|
|
/* Push the flags and return address on the stack */
|
|
*(--stack) = FL_reg(context);
|
|
*(--stack) = CS_reg(context);
|
|
*(--stack) = IP_reg(context) + prefixlen + 2;
|
|
STACK_reg(context) -= 3 * sizeof(WORD);
|
|
/* Jump to the interrupt handler */
|
|
CS_reg(context) = HIWORD(addr);
|
|
EIP_reg(context) = LOWORD(addr);
|
|
}
|
|
return TRUE;
|
|
|
|
case 0xcf: /* iret */
|
|
if (long_op)
|
|
{
|
|
DWORD *stack = (DWORD *)STACK_PTR( context );
|
|
EIP_reg(context) = *stack++;
|
|
CS_reg(context) = *stack++;
|
|
EFL_reg(context) = *stack;
|
|
STACK_reg(context) += 3*sizeof(DWORD); /* Pop the return address and flags */
|
|
}
|
|
else
|
|
{
|
|
WORD *stack = (WORD *)STACK_PTR( context );
|
|
EIP_reg(context) = *stack++;
|
|
CS_reg(context) = *stack++;
|
|
FL_reg(context) = *stack;
|
|
STACK_reg(context) += 3*sizeof(WORD); /* Pop the return address and flags */
|
|
}
|
|
return TRUE;
|
|
|
|
case 0xe4: /* inb al,XX */
|
|
AL_reg(context) = inport( instr[1], 1 );
|
|
EIP_reg(context) += prefixlen + 2;
|
|
return TRUE;
|
|
|
|
case 0xe5: /* in (e)ax,XX */
|
|
if (long_op) EAX_reg(context) = inport( instr[1], 4 );
|
|
else AX_reg(context) = inport( instr[1], 2 );
|
|
EIP_reg(context) += prefixlen + 2;
|
|
return TRUE;
|
|
|
|
case 0xe6: /* outb XX,al */
|
|
outport( instr[1], 1, AL_reg(context) );
|
|
EIP_reg(context) += prefixlen + 2;
|
|
return TRUE;
|
|
|
|
case 0xe7: /* out XX,(e)ax */
|
|
if (long_op) outport( instr[1], 4, EAX_reg(context) );
|
|
else outport( instr[1], 2, AX_reg(context) );
|
|
EIP_reg(context) += prefixlen + 2;
|
|
return TRUE;
|
|
|
|
case 0xec: /* inb al,dx */
|
|
AL_reg(context) = inport( DX_reg(context), 1 );
|
|
EIP_reg(context) += prefixlen + 1;
|
|
return TRUE;
|
|
|
|
case 0xed: /* in (e)ax,dx */
|
|
if (long_op) EAX_reg(context) = inport( DX_reg(context), 4 );
|
|
else AX_reg(context) = inport( DX_reg(context), 2 );
|
|
EIP_reg(context) += prefixlen + 1;
|
|
return TRUE;
|
|
|
|
case 0xee: /* outb dx,al */
|
|
outport( DX_reg(context), 1, AL_reg(context) );
|
|
EIP_reg(context) += prefixlen + 1;
|
|
return TRUE;
|
|
|
|
case 0xef: /* out dx,(e)ax */
|
|
if (long_op) outport( DX_reg(context), 4, EAX_reg(context) );
|
|
else outport( DX_reg(context), 2, AX_reg(context) );
|
|
EIP_reg(context) += prefixlen + 1;
|
|
return TRUE;
|
|
|
|
case 0xfa: /* cli, ignored */
|
|
EIP_reg(context) += prefixlen + 1;
|
|
return TRUE;
|
|
|
|
case 0xfb: /* sti, ignored */
|
|
EIP_reg(context) += prefixlen + 1;
|
|
return TRUE;
|
|
}
|
|
fprintf(stderr, "Unexpected Windows program segfault"
|
|
" - opcode = %x\n", *instr);
|
|
return FALSE; /* Unable to emulate it */
|
|
}
|