Zebediah Figura
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3507615f35
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dbghelp/dwarf: Allow get_context_reg() to handle different register sizes.
Signed-off-by: Zebediah Figura <z.figura12@gmail.com>
Signed-off-by: Alexandre Julliard <julliard@winehq.org>
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2018-08-14 13:55:55 +02:00 |
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Zebediah Figura
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3ce304e601
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dbghelp: Use WOW64_CONTEXT instead of CONTEXT for i386 backend.
Signed-off-by: Zebediah Figura <z.figura12@gmail.com>
Signed-off-by: Alexandre Julliard <julliard@winehq.org>
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2018-08-14 13:55:55 +02:00 |
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André Hentschel
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86864486be
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dbghelp: Map SIMD dwarf registers on ARM64.
Signed-off-by: André Hentschel <nerv@dawncrow.de>
Signed-off-by: Alexandre Julliard <julliard@winehq.org>
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2018-06-28 22:51:12 +02:00 |
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Martin Storsjo
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e0780c258f
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ntdll: Update the ARM64 CONTEXT struct to match Win SDK 10.0.16299.0.
Signed-off-by: Martin Storsjo <martin@martin.st>
Signed-off-by: Alexandre Julliard <julliard@winehq.org>
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2018-03-19 13:13:59 +01:00 |
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Alexandre Julliard
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21c12ddc64
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ntdll: Fix CONTEXT definition for ARM64.
Signed-off-by: Alexandre Julliard <julliard@winehq.org>
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2017-12-05 20:30:01 +01:00 |
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Ken Thomases
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83c1255f66
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dbghelp: Fix mapping of DWARF register numbers on x86 OS X.
For backward compatibility with old, buggy GCC, Apple uses a different register
numbering scheme for the eh_frame section.
See, for reference, the comments near the top of this file from LLDB's source:
https://github.com/llvm-mirror/lldb/blob/release_36/source/Plugins/Process/Utility/RegisterContext_x86.h
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2015-06-29 19:07:51 +09:00 |
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André Hentschel
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bd1f7ef186
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include: Rename 64-bit PState to 32-bit Cpsr on ARM64.
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2015-06-15 14:51:33 +09:00 |
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André Hentschel
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8e0164bd26
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include: Add more ARM64 CV constants.
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2015-05-28 14:20:55 +09:00 |
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André Hentschel
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0d68edf03e
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dbghelp: Fix typo in trace output.
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2015-05-20 22:10:19 +09:00 |
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Frédéric Delanoy
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1d65efe50b
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dbghelp: Use BOOL type where appropriate.
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2013-11-12 12:58:03 +01:00 |
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André Hentschel
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49f59ccf71
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dbghelp: Implement rudimentary stack walk for ARM64.
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2013-01-23 12:44:06 +01:00 |
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André Hentschel
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ce8640cbef
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dbghelp: Add ARM64 support.
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2013-01-16 12:53:16 +01:00 |