msvcrt: Introduce _setfp helper to access floating point status and control words.
Signed-off-by: Piotr Caban <piotr@codeweavers.com> Signed-off-by: Alexandre Julliard <julliard@winehq.org>
This commit is contained in:
Piotr Caban
Alexandre Julliard
parent
f53b2095f3
commit
f1ef14dc17
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@ -5235,37 +5235,148 @@ static BOOL _setfp_sse( unsigned int *cw, unsigned int cw_mask,
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}
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#endif
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#if defined(__i386__) || defined(__x86_64__)
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static BOOL _setfp( unsigned int *cw, unsigned int cw_mask,
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unsigned int *sw, unsigned int sw_mask )
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{
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#if defined(__GNUC__) || defined(__clang__)
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#ifdef __i386__
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unsigned long oldcw = 0, newcw = 0;
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unsigned long oldsw = 0, newsw = 0;
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unsigned int flags;
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cw_mask &= _MCW_EM | _MCW_IC | _MCW_RC | _MCW_PC;
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sw_mask &= _MCW_EM;
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if (sw)
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{
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__asm__ __volatile__( "fstsw %0" : "=m" (newsw) );
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oldsw = newsw;
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flags = 0;
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if (newsw & 0x1) flags |= _SW_INVALID;
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if (newsw & 0x2) flags |= _SW_DENORMAL;
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if (newsw & 0x4) flags |= _SW_ZERODIVIDE;
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if (newsw & 0x8) flags |= _SW_OVERFLOW;
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if (newsw & 0x10) flags |= _SW_UNDERFLOW;
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if (newsw & 0x20) flags |= _SW_INEXACT;
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*sw = (flags & ~sw_mask) | (*sw & sw_mask);
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TRACE("x86 update sw %08x to %08x\n", flags, *sw);
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newsw &= ~0x3f;
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if (*sw & _SW_INVALID) newsw |= 0x1;
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if (*sw & _SW_DENORMAL) newsw |= 0x2;
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if (*sw & _SW_ZERODIVIDE) newsw |= 0x4;
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if (*sw & _SW_OVERFLOW) newsw |= 0x8;
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if (*sw & _SW_UNDERFLOW) newsw |= 0x10;
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if (*sw & _SW_INEXACT) newsw |= 0x20;
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*sw = flags;
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}
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if (cw)
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{
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__asm__ __volatile__( "fstcw %0" : "=m" (newcw) );
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oldcw = newcw;
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flags = 0;
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if (newcw & 0x1) flags |= _EM_INVALID;
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if (newcw & 0x2) flags |= _EM_DENORMAL;
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if (newcw & 0x4) flags |= _EM_ZERODIVIDE;
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if (newcw & 0x8) flags |= _EM_OVERFLOW;
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if (newcw & 0x10) flags |= _EM_UNDERFLOW;
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if (newcw & 0x20) flags |= _EM_INEXACT;
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switch (newcw & 0xc00)
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{
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case 0xc00: flags |= _RC_UP|_RC_DOWN; break;
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case 0x800: flags |= _RC_UP; break;
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case 0x400: flags |= _RC_DOWN; break;
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}
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switch (newcw & 0x300)
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{
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case 0x0: flags |= _PC_24; break;
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case 0x200: flags |= _PC_53; break;
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case 0x300: flags |= _PC_64; break;
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}
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if (newcw & 0x1000) flags |= _IC_AFFINE;
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*cw = (flags & ~cw_mask) | (*cw & cw_mask);
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TRACE("x86 update cw %08x to %08x\n", flags, *cw);
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newcw &= ~0x1e3f;
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if (*cw & _EM_INVALID) newcw |= 0x1;
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if (*cw & _EM_DENORMAL) newcw |= 0x2;
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if (*cw & _EM_ZERODIVIDE) newcw |= 0x4;
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if (*cw & _EM_OVERFLOW) newcw |= 0x8;
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if (*cw & _EM_UNDERFLOW) newcw |= 0x10;
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if (*cw & _EM_INEXACT) newcw |= 0x20;
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switch (*cw & _MCW_RC)
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{
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case _RC_UP|_RC_DOWN: newcw |= 0xc00; break;
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case _RC_UP: newcw |= 0x800; break;
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case _RC_DOWN: newcw |= 0x400; break;
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}
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switch (*cw & _MCW_PC)
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{
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case _PC_64: newcw |= 0x300; break;
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case _PC_53: newcw |= 0x200; break;
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case _PC_24: newcw |= 0x0; break;
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}
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if (*cw & _IC_AFFINE) newcw |= 0x1000;
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}
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if (oldsw != newsw && newsw)
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{
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struct {
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WORD control_word;
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WORD unused1;
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WORD status_word;
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WORD unused2;
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WORD tag_word;
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WORD unused3;
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DWORD instruction_pointer;
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WORD code_segment;
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WORD unused4;
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DWORD operand_addr;
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WORD data_segment;
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WORD unused5;
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} fenv;
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__asm__ __volatile__( "fnstenv %0" : "=m" (fenv) );
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fenv.control_word = newcw;
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fenv.status_word = newsw;
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__asm__ __volatile__( "fldenv %0" : : "m" (fenv) : "st", "st(1)",
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"st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)" );
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return TRUE;
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}
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if (oldsw != newsw)
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__asm__ __volatile__( "fnclex" );
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if (oldcw != newcw)
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__asm__ __volatile__( "fldcw %0" : : "m" (newcw) );
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return TRUE;
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#elif defined(__x86_64__)
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return _setfp_sse(cw, cw_mask, sw, sw_mask);
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#endif
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#else
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FIXME("not implemented\n");
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if (cw) *cw = 0;
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if (sw) *sw = 0;
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return FALSE;
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#endif
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}
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#endif
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/**********************************************************************
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* _statusfp2 (MSVCR80.@)
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*/
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#if defined(__i386__)
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void CDECL _statusfp2( unsigned int *x86_sw, unsigned int *sse2_sw )
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{
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#if defined(__GNUC__) || defined(__clang__)
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unsigned int flags;
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unsigned long fpword;
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if (x86_sw)
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{
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__asm__ __volatile__( "fstsw %0" : "=m" (fpword) );
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flags = 0;
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if (fpword & 0x1) flags |= _SW_INVALID;
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if (fpword & 0x2) flags |= _SW_DENORMAL;
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if (fpword & 0x4) flags |= _SW_ZERODIVIDE;
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if (fpword & 0x8) flags |= _SW_OVERFLOW;
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if (fpword & 0x10) flags |= _SW_UNDERFLOW;
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if (fpword & 0x20) flags |= _SW_INEXACT;
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*x86_sw = flags;
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}
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_setfp(NULL, 0, x86_sw, 0);
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if (!sse2_sw) return;
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if (sse2_supported)
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_setfp_sse(NULL, 0, sse2_sw, 0);
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else *sse2_sw = 0;
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#else
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FIXME( "not implemented\n" );
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#endif
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}
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#endif
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@ -5282,7 +5393,7 @@ unsigned int CDECL _statusfp(void)
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/* FIXME: there's no definition for ambiguous status, just return all status bits for now */
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flags = x86_sw | sse2_sw;
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#elif defined(__x86_64__)
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_setfp_sse(NULL, 0, &flags, 0);
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_setfp(NULL, 0, &flags, 0);
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#elif defined(__aarch64__)
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ULONG_PTR fpsr;
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@ -5315,17 +5426,8 @@ unsigned int CDECL _statusfp(void)
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unsigned int CDECL _clearfp(void)
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{
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unsigned int flags = 0;
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#if (defined(__GNUC__) || defined(__clang__)) && defined(__i386__)
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unsigned long fpword;
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__asm__ __volatile__( "fnstsw %0; fnclex" : "=m" (fpword) );
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if (fpword & 0x1) flags |= _SW_INVALID;
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if (fpword & 0x2) flags |= _SW_DENORMAL;
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if (fpword & 0x4) flags |= _SW_ZERODIVIDE;
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if (fpword & 0x8) flags |= _SW_OVERFLOW;
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if (fpword & 0x10) flags |= _SW_UNDERFLOW;
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if (fpword & 0x20) flags |= _SW_INEXACT;
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#ifdef __i386__
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_setfp(NULL, 0, &flags, _MCW_EM);
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if (sse2_supported)
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{
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unsigned int sse_sw = 0;
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@ -5334,7 +5436,7 @@ unsigned int CDECL _clearfp(void)
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flags |= sse_sw;
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}
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#elif defined(__x86_64__)
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_setfp_sse(NULL, 0, &flags, _MCW_EM);
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_setfp(NULL, 0, &flags, _MCW_EM);
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#elif defined(__aarch64__)
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ULONG_PTR fpsr;
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@ -5414,66 +5516,11 @@ double CDECL _chgsign(double num)
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int CDECL __control87_2( unsigned int newval, unsigned int mask,
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unsigned int *x86_cw, unsigned int *sse2_cw )
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{
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#if defined(__GNUC__) || defined(__clang__)
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unsigned long fpword;
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unsigned int flags;
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if (x86_cw)
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{
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__asm__ __volatile__( "fstcw %0" : "=m" (fpword) );
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/* Convert into mask constants */
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flags = 0;
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if (fpword & 0x1) flags |= _EM_INVALID;
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if (fpword & 0x2) flags |= _EM_DENORMAL;
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if (fpword & 0x4) flags |= _EM_ZERODIVIDE;
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if (fpword & 0x8) flags |= _EM_OVERFLOW;
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if (fpword & 0x10) flags |= _EM_UNDERFLOW;
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if (fpword & 0x20) flags |= _EM_INEXACT;
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switch (fpword & 0xc00)
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{
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case 0xc00: flags |= _RC_UP|_RC_DOWN; break;
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case 0x800: flags |= _RC_UP; break;
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case 0x400: flags |= _RC_DOWN; break;
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}
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switch (fpword & 0x300)
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{
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case 0x0: flags |= _PC_24; break;
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case 0x200: flags |= _PC_53; break;
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case 0x300: flags |= _PC_64; break;
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}
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if (fpword & 0x1000) flags |= _IC_AFFINE;
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TRACE( "x86 flags=%08x newval=%08x mask=%08x\n", flags, newval, mask );
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if (mask)
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{
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flags = (flags & ~mask) | (newval & mask);
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/* Convert (masked) value back to fp word */
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fpword = 0;
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if (flags & _EM_INVALID) fpword |= 0x1;
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if (flags & _EM_DENORMAL) fpword |= 0x2;
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if (flags & _EM_ZERODIVIDE) fpword |= 0x4;
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if (flags & _EM_OVERFLOW) fpword |= 0x8;
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if (flags & _EM_UNDERFLOW) fpword |= 0x10;
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if (flags & _EM_INEXACT) fpword |= 0x20;
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switch (flags & _MCW_RC)
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{
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case _RC_UP|_RC_DOWN: fpword |= 0xc00; break;
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case _RC_UP: fpword |= 0x800; break;
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case _RC_DOWN: fpword |= 0x400; break;
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}
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switch (flags & _MCW_PC)
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{
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case _PC_64: fpword |= 0x300; break;
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case _PC_53: fpword |= 0x200; break;
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case _PC_24: fpword |= 0x0; break;
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}
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if (flags & _IC_AFFINE) fpword |= 0x1000;
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__asm__ __volatile__( "fldcw %0" : : "m" (fpword) );
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}
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*x86_cw = flags;
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*x86_cw = newval;
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if (!_setfp(x86_cw, mask, NULL, 0))
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return 0;
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}
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if (!sse2_cw) return 1;
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@ -5487,10 +5534,6 @@ int CDECL __control87_2( unsigned int newval, unsigned int mask,
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else *sse2_cw = 0;
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return 1;
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#else
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FIXME( "not implemented\n" );
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return 0;
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#endif
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}
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#endif
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@ -5509,7 +5552,7 @@ unsigned int CDECL _control87(unsigned int newval, unsigned int mask)
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flags |= sse2_cw;
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#elif defined(__x86_64__)
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flags = newval;
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_setfp_sse(&flags, mask, NULL, 0);
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_setfp(&flags, mask, NULL, 0);
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#elif defined(__aarch64__)
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ULONG_PTR fpcr;
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@ -5747,7 +5790,7 @@ int CDECL fegetenv(fenv_t *env)
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env->_Fe_stat = fenv_encode(0, _statusfp());
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#else
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env->_Fe_ctl = _controlfp(0, 0) & (_EM_INEXACT | _EM_UNDERFLOW |
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_EM_OVERFLOW | _EM_ZERODIVIDE | _EM_INVALID | _RC_CHOP);
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_EM_OVERFLOW | _EM_ZERODIVIDE | _EM_INVALID | _MCW_RC);
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env->_Fe_stat = _statusfp();
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#endif
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return 0;
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@ -5911,7 +5954,7 @@ void CDECL _fpreset(void)
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}
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#elif defined(__x86_64__)
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unsigned int cw = _MCW_EM, sw = 0;
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_setfp_sse(&cw, ~0, &sw, ~0);
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_setfp(&cw, ~0, &sw, ~0);
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#else
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FIXME( "not implemented\n" );
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#endif
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@ -5923,24 +5966,9 @@ void CDECL _fpreset(void)
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*/
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int CDECL fesetenv(const fenv_t *env)
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{
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#if (defined(__GNUC__) || defined(__clang__)) && (defined(__i386__) || defined(__x86_64__))
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unsigned int x87_cw, sse_cw, x87_stat, sse_stat;
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#ifdef __i386__
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struct {
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WORD control_word;
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WORD unused1;
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WORD status_word;
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WORD unused2;
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WORD tag_word;
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WORD unused3;
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DWORD instruction_pointer;
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WORD code_segment;
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WORD unused4;
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DWORD operand_addr;
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WORD data_segment;
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WORD unused5;
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} fenv;
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#endif
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#if defined(__i386__) || defined(__x86_64__)
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unsigned int x87_cw, cw, x87_stat, stat;
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unsigned int mask;
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TRACE( "(%p)\n", env );
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@ -5949,60 +5977,32 @@ int CDECL fesetenv(const fenv_t *env)
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return 0;
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}
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if (!fenv_decode(env->_Fe_ctl, &x87_cw, &sse_cw))
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if (!fenv_decode(env->_Fe_ctl, &x87_cw, &cw))
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return 1;
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if (!fenv_decode(env->_Fe_stat, &x87_stat, &sse_stat))
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if (!fenv_decode(env->_Fe_stat, &x87_stat, &stat))
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return 1;
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#if _MSVCR_VER >= 140
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mask = ~0;
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#else
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mask = _EM_INEXACT | _EM_UNDERFLOW | _EM_OVERFLOW
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| _EM_ZERODIVIDE | _EM_INVALID | _MCW_RC;
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#endif
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#ifdef __i386__
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__asm__ __volatile__( "fnstenv %0" : "=m" (fenv) );
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fenv.control_word &= ~0xc3d;
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#if _MSVCR_VER>=140
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fenv.control_word &= ~0x1302;
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#endif
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if (x87_cw & _EM_INVALID) fenv.control_word |= 0x1;
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if (x87_cw & _EM_ZERODIVIDE) fenv.control_word |= 0x4;
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if (x87_cw & _EM_OVERFLOW) fenv.control_word |= 0x8;
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if (x87_cw & _EM_UNDERFLOW) fenv.control_word |= 0x10;
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if (x87_cw & _EM_INEXACT) fenv.control_word |= 0x20;
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switch (x87_cw & _MCW_RC)
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{
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case _RC_UP|_RC_DOWN: fenv.control_word |= 0xc00; break;
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case _RC_UP: fenv.control_word |= 0x800; break;
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case _RC_DOWN: fenv.control_word |= 0x400; break;
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}
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#if _MSVCR_VER>=140
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if (x87_cw & _EM_DENORMAL) fenv.control_word |= 0x2;
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switch (x87_cw & _MCW_PC)
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{
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case _PC_64: fenv.control_word |= 0x300; break;
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case _PC_53: fenv.control_word |= 0x200; break;
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case _PC_24: fenv.control_word |= 0x0; break;
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}
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if (x87_cw & _IC_AFFINE) fenv.control_word |= 0x1000;
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#endif
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fenv.status_word &= ~0x3f;
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if (x87_stat & _SW_INVALID) fenv.status_word |= 0x1;
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if (x87_stat & _SW_DENORMAL) fenv.status_word |= 0x2;
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if (x87_stat & _SW_ZERODIVIDE) fenv.status_word |= 0x4;
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if (x87_stat & _SW_OVERFLOW) fenv.status_word |= 0x8;
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if (x87_stat & _SW_UNDERFLOW) fenv.status_word |= 0x10;
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if (x87_stat & _SW_INEXACT) fenv.status_word |= 0x20;
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__asm__ __volatile__( "fldenv %0" : : "m" (fenv) : "st", "st(1)",
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"st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)" );
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#endif
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if (!_setfp(&x87_cw, mask, &x87_stat, ~0))
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return 1;
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if (sse2_supported)
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{
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||||
if(!_setfp_sse(&sse_cw, _MSVCR_VER>=140 ? ~0 :
|
||||
~_EM_DENORMAL & (_MCW_EM | _MCW_RC), &sse_stat, _MCW_EM))
|
||||
if (!_setfp_sse(&cw, mask, &stat, ~0))
|
||||
return 1;
|
||||
}
|
||||
|
||||
return 0;
|
||||
#else
|
||||
if (!_setfp(&cw, mask, &stat, ~0))
|
||||
return 1;
|
||||
return 0;
|
||||
#endif
|
||||
#elif defined(__aarch64__)
|
||||
ULONG_PTR fpsr;
|
||||
unsigned int tmp, fp_cw, fp_stat;
|
||||
|
|
@ -6057,8 +6057,8 @@ int CDECL fesetenv(const fenv_t *env)
|
|||
return 0;
|
||||
#else
|
||||
FIXME( "not implemented\n" );
|
||||
#endif
|
||||
return 1;
|
||||
#endif
|
||||
}
|
||||
#endif
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue