winedbg/gdbproxy: Remove unnecessary checks for supported context flags.
And simplify the assignment to use CONTEXT_ALL instead. If we don't support reading from a register then we just ignore its value. Signed-off-by: Zebediah Figura <zfigura@codeweavers.com> Signed-off-by: Alexandre Julliard <julliard@winehq.org>
This commit is contained in:
Zebediah Figura
Alexandre Julliard
parent
42bbeedbe4
commit
b459c88caa
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@ -199,10 +199,9 @@ struct cpu_register
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size_t ctx_offset;
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size_t ctx_length;
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size_t gdb_length;
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ULONG ctx_flags;
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};
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#define REG(r,gs,m) {FIELD_OFFSET(CONTEXT, r), sizeof(((CONTEXT*)NULL)->r), gs, m}
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#define REG(r,gs) {FIELD_OFFSET(CONTEXT, r), sizeof(((CONTEXT*)NULL)->r), gs}
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#ifdef __i386__
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typedef struct DECLSPEC_ALIGN(16) _M128A {
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@ -231,185 +230,185 @@ typedef struct _XMM_SAVE_AREA32 {
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static const char target_xml[] = "";
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static struct cpu_register cpu_register_map[] = {
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REG(Eax, 4, CONTEXT_INTEGER),
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REG(Ecx, 4, CONTEXT_INTEGER),
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REG(Edx, 4, CONTEXT_INTEGER),
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REG(Ebx, 4, CONTEXT_INTEGER),
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REG(Esp, 4, CONTEXT_CONTROL),
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REG(Ebp, 4, CONTEXT_CONTROL),
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REG(Esi, 4, CONTEXT_INTEGER),
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REG(Edi, 4, CONTEXT_INTEGER),
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REG(Eip, 4, CONTEXT_CONTROL),
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REG(EFlags, 4, CONTEXT_CONTROL),
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REG(SegCs, 4, CONTEXT_CONTROL),
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REG(SegSs, 4, CONTEXT_SEGMENTS),
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REG(SegDs, 4, CONTEXT_SEGMENTS),
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REG(SegEs, 4, CONTEXT_SEGMENTS),
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REG(SegFs, 4, CONTEXT_SEGMENTS),
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REG(SegGs, 4, CONTEXT_SEGMENTS),
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{ FIELD_OFFSET(CONTEXT, FloatSave.RegisterArea[ 0]), 10, 10, CONTEXT_FLOATING_POINT },
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{ FIELD_OFFSET(CONTEXT, FloatSave.RegisterArea[10]), 10, 10, CONTEXT_FLOATING_POINT },
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{ FIELD_OFFSET(CONTEXT, FloatSave.RegisterArea[20]), 10, 10, CONTEXT_FLOATING_POINT },
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{ FIELD_OFFSET(CONTEXT, FloatSave.RegisterArea[30]), 10, 10, CONTEXT_FLOATING_POINT },
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{ FIELD_OFFSET(CONTEXT, FloatSave.RegisterArea[40]), 10, 10, CONTEXT_FLOATING_POINT },
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{ FIELD_OFFSET(CONTEXT, FloatSave.RegisterArea[50]), 10, 10, CONTEXT_FLOATING_POINT },
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{ FIELD_OFFSET(CONTEXT, FloatSave.RegisterArea[60]), 10, 10, CONTEXT_FLOATING_POINT },
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{ FIELD_OFFSET(CONTEXT, FloatSave.RegisterArea[70]), 10, 10, CONTEXT_FLOATING_POINT },
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{ FIELD_OFFSET(CONTEXT, FloatSave.ControlWord), 2, 4, CONTEXT_FLOATING_POINT },
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{ FIELD_OFFSET(CONTEXT, FloatSave.StatusWord), 2, 4, CONTEXT_FLOATING_POINT },
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{ FIELD_OFFSET(CONTEXT, FloatSave.TagWord), 2, 4, CONTEXT_FLOATING_POINT },
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{ FIELD_OFFSET(CONTEXT, FloatSave.ErrorSelector), 2, 4, CONTEXT_FLOATING_POINT },
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REG(FloatSave.ErrorOffset, 4, CONTEXT_FLOATING_POINT ),
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{ FIELD_OFFSET(CONTEXT, FloatSave.DataSelector), 2, 4, CONTEXT_FLOATING_POINT },
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REG(FloatSave.DataOffset, 4, CONTEXT_FLOATING_POINT ),
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{ FIELD_OFFSET(CONTEXT, FloatSave.ErrorSelector)+2, 2, 4, CONTEXT_FLOATING_POINT },
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{ FIELD_OFFSET(CONTEXT, ExtendedRegisters) + FIELD_OFFSET(XMM_SAVE_AREA32, XmmRegisters[0]), 16, 16, CONTEXT_EXTENDED_REGISTERS },
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{ FIELD_OFFSET(CONTEXT, ExtendedRegisters) + FIELD_OFFSET(XMM_SAVE_AREA32, XmmRegisters[1]), 16, 16, CONTEXT_EXTENDED_REGISTERS },
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{ FIELD_OFFSET(CONTEXT, ExtendedRegisters) + FIELD_OFFSET(XMM_SAVE_AREA32, XmmRegisters[2]), 16, 16, CONTEXT_EXTENDED_REGISTERS },
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{ FIELD_OFFSET(CONTEXT, ExtendedRegisters) + FIELD_OFFSET(XMM_SAVE_AREA32, XmmRegisters[3]), 16, 16, CONTEXT_EXTENDED_REGISTERS },
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{ FIELD_OFFSET(CONTEXT, ExtendedRegisters) + FIELD_OFFSET(XMM_SAVE_AREA32, XmmRegisters[4]), 16, 16, CONTEXT_EXTENDED_REGISTERS },
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{ FIELD_OFFSET(CONTEXT, ExtendedRegisters) + FIELD_OFFSET(XMM_SAVE_AREA32, XmmRegisters[5]), 16, 16, CONTEXT_EXTENDED_REGISTERS },
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{ FIELD_OFFSET(CONTEXT, ExtendedRegisters) + FIELD_OFFSET(XMM_SAVE_AREA32, XmmRegisters[6]), 16, 16, CONTEXT_EXTENDED_REGISTERS },
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{ FIELD_OFFSET(CONTEXT, ExtendedRegisters) + FIELD_OFFSET(XMM_SAVE_AREA32, XmmRegisters[7]), 16, 16, CONTEXT_EXTENDED_REGISTERS },
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{ FIELD_OFFSET(CONTEXT, ExtendedRegisters) + FIELD_OFFSET(XMM_SAVE_AREA32, MxCsr), 4, 4, CONTEXT_EXTENDED_REGISTERS },
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REG(Eax, 4),
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REG(Ecx, 4),
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REG(Edx, 4),
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REG(Ebx, 4),
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REG(Esp, 4),
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REG(Ebp, 4),
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REG(Esi, 4),
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REG(Edi, 4),
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REG(Eip, 4),
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REG(EFlags, 4),
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REG(SegCs, 4),
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REG(SegSs, 4),
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REG(SegDs, 4),
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REG(SegEs, 4),
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REG(SegFs, 4),
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REG(SegGs, 4),
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{ FIELD_OFFSET(CONTEXT, FloatSave.RegisterArea[ 0]), 10, 10 },
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{ FIELD_OFFSET(CONTEXT, FloatSave.RegisterArea[10]), 10, 10 },
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{ FIELD_OFFSET(CONTEXT, FloatSave.RegisterArea[20]), 10, 10 },
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{ FIELD_OFFSET(CONTEXT, FloatSave.RegisterArea[30]), 10, 10 },
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{ FIELD_OFFSET(CONTEXT, FloatSave.RegisterArea[40]), 10, 10 },
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{ FIELD_OFFSET(CONTEXT, FloatSave.RegisterArea[50]), 10, 10 },
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{ FIELD_OFFSET(CONTEXT, FloatSave.RegisterArea[60]), 10, 10 },
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{ FIELD_OFFSET(CONTEXT, FloatSave.RegisterArea[70]), 10, 10 },
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{ FIELD_OFFSET(CONTEXT, FloatSave.ControlWord), 2, 4 },
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{ FIELD_OFFSET(CONTEXT, FloatSave.StatusWord), 2, 4 },
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{ FIELD_OFFSET(CONTEXT, FloatSave.TagWord), 2, 4 },
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{ FIELD_OFFSET(CONTEXT, FloatSave.ErrorSelector), 2, 4 },
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REG(FloatSave.ErrorOffset, 4 ),
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{ FIELD_OFFSET(CONTEXT, FloatSave.DataSelector), 2, 4 },
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REG(FloatSave.DataOffset, 4 ),
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{ FIELD_OFFSET(CONTEXT, FloatSave.ErrorSelector)+2, 2, 4 },
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{ FIELD_OFFSET(CONTEXT, ExtendedRegisters) + FIELD_OFFSET(XMM_SAVE_AREA32, XmmRegisters[0]), 16, 16 },
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{ FIELD_OFFSET(CONTEXT, ExtendedRegisters) + FIELD_OFFSET(XMM_SAVE_AREA32, XmmRegisters[1]), 16, 16 },
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{ FIELD_OFFSET(CONTEXT, ExtendedRegisters) + FIELD_OFFSET(XMM_SAVE_AREA32, XmmRegisters[2]), 16, 16 },
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{ FIELD_OFFSET(CONTEXT, ExtendedRegisters) + FIELD_OFFSET(XMM_SAVE_AREA32, XmmRegisters[3]), 16, 16 },
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{ FIELD_OFFSET(CONTEXT, ExtendedRegisters) + FIELD_OFFSET(XMM_SAVE_AREA32, XmmRegisters[4]), 16, 16 },
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{ FIELD_OFFSET(CONTEXT, ExtendedRegisters) + FIELD_OFFSET(XMM_SAVE_AREA32, XmmRegisters[5]), 16, 16 },
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{ FIELD_OFFSET(CONTEXT, ExtendedRegisters) + FIELD_OFFSET(XMM_SAVE_AREA32, XmmRegisters[6]), 16, 16 },
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{ FIELD_OFFSET(CONTEXT, ExtendedRegisters) + FIELD_OFFSET(XMM_SAVE_AREA32, XmmRegisters[7]), 16, 16 },
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{ FIELD_OFFSET(CONTEXT, ExtendedRegisters) + FIELD_OFFSET(XMM_SAVE_AREA32, MxCsr), 4, 4 },
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};
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#elif defined(__powerpc__)
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static const char target_xml[] = "";
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static struct cpu_register cpu_register_map[] = {
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REG(Gpr0, 4, CONTEXT_INTEGER),
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REG(Gpr1, 4, CONTEXT_INTEGER),
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REG(Gpr2, 4, CONTEXT_INTEGER),
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REG(Gpr3, 4, CONTEXT_INTEGER),
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REG(Gpr4, 4, CONTEXT_INTEGER),
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REG(Gpr5, 4, CONTEXT_INTEGER),
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REG(Gpr6, 4, CONTEXT_INTEGER),
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REG(Gpr7, 4, CONTEXT_INTEGER),
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REG(Gpr8, 4, CONTEXT_INTEGER),
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REG(Gpr9, 4, CONTEXT_INTEGER),
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REG(Gpr10, 4, CONTEXT_INTEGER),
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REG(Gpr11, 4, CONTEXT_INTEGER),
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REG(Gpr12, 4, CONTEXT_INTEGER),
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REG(Gpr13, 4, CONTEXT_INTEGER),
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REG(Gpr14, 4, CONTEXT_INTEGER),
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REG(Gpr15, 4, CONTEXT_INTEGER),
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REG(Gpr16, 4, CONTEXT_INTEGER),
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REG(Gpr17, 4, CONTEXT_INTEGER),
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REG(Gpr18, 4, CONTEXT_INTEGER),
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REG(Gpr19, 4, CONTEXT_INTEGER),
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REG(Gpr20, 4, CONTEXT_INTEGER),
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REG(Gpr21, 4, CONTEXT_INTEGER),
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REG(Gpr22, 4, CONTEXT_INTEGER),
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REG(Gpr23, 4, CONTEXT_INTEGER),
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REG(Gpr24, 4, CONTEXT_INTEGER),
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REG(Gpr25, 4, CONTEXT_INTEGER),
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REG(Gpr26, 4, CONTEXT_INTEGER),
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REG(Gpr27, 4, CONTEXT_INTEGER),
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REG(Gpr28, 4, CONTEXT_INTEGER),
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REG(Gpr29, 4, CONTEXT_INTEGER),
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REG(Gpr30, 4, CONTEXT_INTEGER),
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REG(Gpr31, 4, CONTEXT_INTEGER),
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REG(Fpr0, 4, CONTEXT_FLOATING_POINT),
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REG(Fpr1, 4, CONTEXT_FLOATING_POINT),
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REG(Fpr2, 4, CONTEXT_FLOATING_POINT),
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REG(Fpr3, 4, CONTEXT_FLOATING_POINT),
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REG(Fpr4, 4, CONTEXT_FLOATING_POINT),
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REG(Fpr5, 4, CONTEXT_FLOATING_POINT),
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REG(Fpr6, 4, CONTEXT_FLOATING_POINT),
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REG(Fpr7, 4, CONTEXT_FLOATING_POINT),
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REG(Fpr8, 4, CONTEXT_FLOATING_POINT),
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REG(Fpr9, 4, CONTEXT_FLOATING_POINT),
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REG(Fpr10, 4, CONTEXT_FLOATING_POINT),
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REG(Fpr11, 4, CONTEXT_FLOATING_POINT),
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REG(Fpr12, 4, CONTEXT_FLOATING_POINT),
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REG(Fpr13, 4, CONTEXT_FLOATING_POINT),
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REG(Fpr14, 4, CONTEXT_FLOATING_POINT),
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REG(Fpr15, 4, CONTEXT_FLOATING_POINT),
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REG(Fpr16, 4, CONTEXT_FLOATING_POINT),
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REG(Fpr17, 4, CONTEXT_FLOATING_POINT),
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REG(Fpr18, 4, CONTEXT_FLOATING_POINT),
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REG(Fpr19, 4, CONTEXT_FLOATING_POINT),
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REG(Fpr20, 4, CONTEXT_FLOATING_POINT),
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REG(Fpr21, 4, CONTEXT_FLOATING_POINT),
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REG(Fpr22, 4, CONTEXT_FLOATING_POINT),
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REG(Fpr23, 4, CONTEXT_FLOATING_POINT),
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REG(Fpr24, 4, CONTEXT_FLOATING_POINT),
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REG(Fpr25, 4, CONTEXT_FLOATING_POINT),
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REG(Fpr26, 4, CONTEXT_FLOATING_POINT),
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REG(Fpr27, 4, CONTEXT_FLOATING_POINT),
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REG(Fpr28, 4, CONTEXT_FLOATING_POINT),
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REG(Fpr29, 4, CONTEXT_FLOATING_POINT),
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REG(Fpr30, 4, CONTEXT_FLOATING_POINT),
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REG(Fpr31, 4, CONTEXT_FLOATING_POINT),
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REG(Gpr0, 4),
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REG(Gpr1, 4),
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REG(Gpr2, 4),
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REG(Gpr3, 4),
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REG(Gpr4, 4),
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REG(Gpr5, 4),
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REG(Gpr6, 4),
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REG(Gpr7, 4),
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REG(Gpr8, 4),
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REG(Gpr9, 4),
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REG(Gpr10, 4),
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REG(Gpr11, 4),
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REG(Gpr12, 4),
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REG(Gpr13, 4),
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REG(Gpr14, 4),
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REG(Gpr15, 4),
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REG(Gpr16, 4),
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REG(Gpr17, 4),
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REG(Gpr18, 4),
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REG(Gpr19, 4),
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REG(Gpr20, 4),
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REG(Gpr21, 4),
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REG(Gpr22, 4),
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REG(Gpr23, 4),
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REG(Gpr24, 4),
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REG(Gpr25, 4),
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REG(Gpr26, 4),
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REG(Gpr27, 4),
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REG(Gpr28, 4),
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REG(Gpr29, 4),
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REG(Gpr30, 4),
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REG(Gpr31, 4),
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REG(Fpr0, 4),
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REG(Fpr1, 4),
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REG(Fpr2, 4),
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REG(Fpr3, 4),
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REG(Fpr4, 4),
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REG(Fpr5, 4),
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REG(Fpr6, 4),
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REG(Fpr7, 4),
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REG(Fpr8, 4),
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REG(Fpr9, 4),
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REG(Fpr10, 4),
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REG(Fpr11, 4),
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REG(Fpr12, 4),
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REG(Fpr13, 4),
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REG(Fpr14, 4),
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REG(Fpr15, 4),
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REG(Fpr16, 4),
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REG(Fpr17, 4),
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REG(Fpr18, 4),
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REG(Fpr19, 4),
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REG(Fpr20, 4),
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REG(Fpr21, 4),
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REG(Fpr22, 4),
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REG(Fpr23, 4),
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REG(Fpr24, 4),
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REG(Fpr25, 4),
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REG(Fpr26, 4),
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REG(Fpr27, 4),
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REG(Fpr28, 4),
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REG(Fpr29, 4),
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REG(Fpr30, 4),
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REG(Fpr31, 4),
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REG(Iar, 4, CONTEXT_CONTROL),
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REG(Msr, 4, CONTEXT_CONTROL),
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REG(Cr, 4, CONTEXT_INTEGER),
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REG(Lr, 4, CONTEXT_CONTROL),
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REG(Ctr, 4, CONTEXT_CONTROL),
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REG(Xer, 4, CONTEXT_INTEGER),
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REG(Iar, 4),
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REG(Msr, 4),
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REG(Cr, 4),
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REG(Lr, 4),
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REG(Ctr, 4),
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REG(Xer, 4),
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/* FIXME: MQ is missing? FIELD_OFFSET(CONTEXT, Mq), */
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/* see gdb/nlm/ppc.c */
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};
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#elif defined(__x86_64__)
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static const char target_xml[] = "";
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static struct cpu_register cpu_register_map[] = {
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REG(Rax, 8, CONTEXT_INTEGER),
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REG(Rbx, 8, CONTEXT_INTEGER),
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REG(Rcx, 8, CONTEXT_INTEGER),
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REG(Rdx, 8, CONTEXT_INTEGER),
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REG(Rsi, 8, CONTEXT_INTEGER),
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REG(Rdi, 8, CONTEXT_INTEGER),
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REG(Rbp, 8, CONTEXT_INTEGER),
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REG(Rsp, 8, CONTEXT_INTEGER),
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REG(R8, 8, CONTEXT_INTEGER),
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REG(R9, 8, CONTEXT_INTEGER),
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REG(R10, 8, CONTEXT_INTEGER),
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REG(R11, 8, CONTEXT_INTEGER),
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REG(R12, 8, CONTEXT_INTEGER),
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REG(R13, 8, CONTEXT_INTEGER),
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REG(R14, 8, CONTEXT_INTEGER),
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REG(R15, 8, CONTEXT_INTEGER),
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REG(Rip, 8, CONTEXT_CONTROL),
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REG(EFlags, 4, CONTEXT_CONTROL),
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REG(SegCs, 4, CONTEXT_CONTROL),
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REG(SegSs, 4, CONTEXT_CONTROL),
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REG(SegDs, 4, CONTEXT_SEGMENTS),
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REG(SegEs, 4, CONTEXT_SEGMENTS),
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REG(SegFs, 4, CONTEXT_SEGMENTS),
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REG(SegGs, 4, CONTEXT_SEGMENTS),
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{ FIELD_OFFSET(CONTEXT, u.FltSave.FloatRegisters[ 0]), 10, 10, CONTEXT_FLOATING_POINT },
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{ FIELD_OFFSET(CONTEXT, u.FltSave.FloatRegisters[ 1]), 10, 10, CONTEXT_FLOATING_POINT },
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{ FIELD_OFFSET(CONTEXT, u.FltSave.FloatRegisters[ 2]), 10, 10, CONTEXT_FLOATING_POINT },
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{ FIELD_OFFSET(CONTEXT, u.FltSave.FloatRegisters[ 3]), 10, 10, CONTEXT_FLOATING_POINT },
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{ FIELD_OFFSET(CONTEXT, u.FltSave.FloatRegisters[ 4]), 10, 10, CONTEXT_FLOATING_POINT },
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{ FIELD_OFFSET(CONTEXT, u.FltSave.FloatRegisters[ 5]), 10, 10, CONTEXT_FLOATING_POINT },
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{ FIELD_OFFSET(CONTEXT, u.FltSave.FloatRegisters[ 6]), 10, 10, CONTEXT_FLOATING_POINT },
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{ FIELD_OFFSET(CONTEXT, u.FltSave.FloatRegisters[ 7]), 10, 10, CONTEXT_FLOATING_POINT },
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REG(u.FltSave.ControlWord, 4, CONTEXT_FLOATING_POINT),
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REG(u.FltSave.StatusWord, 4, CONTEXT_FLOATING_POINT),
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REG(u.FltSave.TagWord, 4, CONTEXT_FLOATING_POINT),
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REG(u.FltSave.ErrorSelector, 4, CONTEXT_FLOATING_POINT),
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REG(u.FltSave.ErrorOffset, 4, CONTEXT_FLOATING_POINT),
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REG(u.FltSave.DataSelector, 4, CONTEXT_FLOATING_POINT),
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REG(u.FltSave.DataOffset, 4, CONTEXT_FLOATING_POINT),
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REG(u.FltSave.ErrorOpcode, 4, CONTEXT_FLOATING_POINT),
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REG(u.s.Xmm0, 16, CONTEXT_FLOATING_POINT),
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REG(u.s.Xmm1, 16, CONTEXT_FLOATING_POINT),
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REG(u.s.Xmm2, 16, CONTEXT_FLOATING_POINT),
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REG(u.s.Xmm3, 16, CONTEXT_FLOATING_POINT),
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REG(u.s.Xmm4, 16, CONTEXT_FLOATING_POINT),
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REG(u.s.Xmm5, 16, CONTEXT_FLOATING_POINT),
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REG(u.s.Xmm6, 16, CONTEXT_FLOATING_POINT),
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REG(u.s.Xmm7, 16, CONTEXT_FLOATING_POINT),
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REG(u.s.Xmm8, 16, CONTEXT_FLOATING_POINT),
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REG(u.s.Xmm9, 16, CONTEXT_FLOATING_POINT),
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REG(u.s.Xmm10, 16, CONTEXT_FLOATING_POINT),
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REG(u.s.Xmm11, 16, CONTEXT_FLOATING_POINT),
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REG(u.s.Xmm12, 16, CONTEXT_FLOATING_POINT),
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REG(u.s.Xmm13, 16, CONTEXT_FLOATING_POINT),
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REG(u.s.Xmm14, 16, CONTEXT_FLOATING_POINT),
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REG(u.s.Xmm15, 16, CONTEXT_FLOATING_POINT),
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REG(u.FltSave.MxCsr, 4, CONTEXT_FLOATING_POINT),
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REG(Rax, 8),
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REG(Rbx, 8),
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REG(Rcx, 8),
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REG(Rdx, 8),
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REG(Rsi, 8),
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REG(Rdi, 8),
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REG(Rbp, 8),
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REG(Rsp, 8),
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REG(R8, 8),
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REG(R9, 8),
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REG(R10, 8),
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REG(R11, 8),
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REG(R12, 8),
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REG(R13, 8),
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REG(R14, 8),
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REG(R15, 8),
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REG(Rip, 8),
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REG(EFlags, 4),
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REG(SegCs, 4),
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REG(SegSs, 4),
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REG(SegDs, 4),
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REG(SegEs, 4),
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REG(SegFs, 4),
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REG(SegGs, 4),
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{ FIELD_OFFSET(CONTEXT, u.FltSave.FloatRegisters[ 0]), 10, 10 },
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{ FIELD_OFFSET(CONTEXT, u.FltSave.FloatRegisters[ 1]), 10, 10 },
|
||||
{ FIELD_OFFSET(CONTEXT, u.FltSave.FloatRegisters[ 2]), 10, 10 },
|
||||
{ FIELD_OFFSET(CONTEXT, u.FltSave.FloatRegisters[ 3]), 10, 10 },
|
||||
{ FIELD_OFFSET(CONTEXT, u.FltSave.FloatRegisters[ 4]), 10, 10 },
|
||||
{ FIELD_OFFSET(CONTEXT, u.FltSave.FloatRegisters[ 5]), 10, 10 },
|
||||
{ FIELD_OFFSET(CONTEXT, u.FltSave.FloatRegisters[ 6]), 10, 10 },
|
||||
{ FIELD_OFFSET(CONTEXT, u.FltSave.FloatRegisters[ 7]), 10, 10 },
|
||||
REG(u.FltSave.ControlWord, 4),
|
||||
REG(u.FltSave.StatusWord, 4),
|
||||
REG(u.FltSave.TagWord, 4),
|
||||
REG(u.FltSave.ErrorSelector, 4),
|
||||
REG(u.FltSave.ErrorOffset, 4),
|
||||
REG(u.FltSave.DataSelector, 4),
|
||||
REG(u.FltSave.DataOffset, 4),
|
||||
REG(u.FltSave.ErrorOpcode, 4),
|
||||
REG(u.s.Xmm0, 16),
|
||||
REG(u.s.Xmm1, 16),
|
||||
REG(u.s.Xmm2, 16),
|
||||
REG(u.s.Xmm3, 16),
|
||||
REG(u.s.Xmm4, 16),
|
||||
REG(u.s.Xmm5, 16),
|
||||
REG(u.s.Xmm6, 16),
|
||||
REG(u.s.Xmm7, 16),
|
||||
REG(u.s.Xmm8, 16),
|
||||
REG(u.s.Xmm9, 16),
|
||||
REG(u.s.Xmm10, 16),
|
||||
REG(u.s.Xmm11, 16),
|
||||
REG(u.s.Xmm12, 16),
|
||||
REG(u.s.Xmm13, 16),
|
||||
REG(u.s.Xmm14, 16),
|
||||
REG(u.s.Xmm15, 16),
|
||||
REG(u.FltSave.MxCsr, 4),
|
||||
};
|
||||
#elif defined(__arm__)
|
||||
static const char target_xml[] =
|
||||
|
|
@ -435,61 +434,61 @@ static const char target_xml[] =
|
|||
"</feature></target>\n";
|
||||
|
||||
static struct cpu_register cpu_register_map[] = {
|
||||
REG(R0, 4, CONTEXT_INTEGER),
|
||||
REG(R1, 4, CONTEXT_INTEGER),
|
||||
REG(R2, 4, CONTEXT_INTEGER),
|
||||
REG(R3, 4, CONTEXT_INTEGER),
|
||||
REG(R4, 4, CONTEXT_INTEGER),
|
||||
REG(R5, 4, CONTEXT_INTEGER),
|
||||
REG(R6, 4, CONTEXT_INTEGER),
|
||||
REG(R7, 4, CONTEXT_INTEGER),
|
||||
REG(R8, 4, CONTEXT_INTEGER),
|
||||
REG(R9, 4, CONTEXT_INTEGER),
|
||||
REG(R10, 4, CONTEXT_INTEGER),
|
||||
REG(R11, 4, CONTEXT_INTEGER),
|
||||
REG(R12, 4, CONTEXT_INTEGER),
|
||||
REG(Sp, 4, CONTEXT_CONTROL),
|
||||
REG(Lr, 4, CONTEXT_CONTROL),
|
||||
REG(Pc, 4, CONTEXT_CONTROL),
|
||||
REG(Cpsr, 4, CONTEXT_CONTROL),
|
||||
REG(R0, 4),
|
||||
REG(R1, 4),
|
||||
REG(R2, 4),
|
||||
REG(R3, 4),
|
||||
REG(R4, 4),
|
||||
REG(R5, 4),
|
||||
REG(R6, 4),
|
||||
REG(R7, 4),
|
||||
REG(R8, 4),
|
||||
REG(R9, 4),
|
||||
REG(R10, 4),
|
||||
REG(R11, 4),
|
||||
REG(R12, 4),
|
||||
REG(Sp, 4),
|
||||
REG(Lr, 4),
|
||||
REG(Pc, 4),
|
||||
REG(Cpsr, 4),
|
||||
};
|
||||
#elif defined(__aarch64__)
|
||||
static const char target_xml[] = "";
|
||||
static struct cpu_register cpu_register_map[] = {
|
||||
REG(Cpsr, 4, CONTEXT_CONTROL),
|
||||
REG(u.s.X0, 8, CONTEXT_INTEGER),
|
||||
REG(u.s.X1, 8, CONTEXT_INTEGER),
|
||||
REG(u.s.X2, 8, CONTEXT_INTEGER),
|
||||
REG(u.s.X3, 8, CONTEXT_INTEGER),
|
||||
REG(u.s.X4, 8, CONTEXT_INTEGER),
|
||||
REG(u.s.X5, 8, CONTEXT_INTEGER),
|
||||
REG(u.s.X6, 8, CONTEXT_INTEGER),
|
||||
REG(u.s.X7, 8, CONTEXT_INTEGER),
|
||||
REG(u.s.X8, 8, CONTEXT_INTEGER),
|
||||
REG(u.s.X9, 8, CONTEXT_INTEGER),
|
||||
REG(u.s.X10, 8, CONTEXT_INTEGER),
|
||||
REG(u.s.X11, 8, CONTEXT_INTEGER),
|
||||
REG(u.s.X12, 8, CONTEXT_INTEGER),
|
||||
REG(u.s.X13, 8, CONTEXT_INTEGER),
|
||||
REG(u.s.X14, 8, CONTEXT_INTEGER),
|
||||
REG(u.s.X15, 8, CONTEXT_INTEGER),
|
||||
REG(u.s.X16, 8, CONTEXT_INTEGER),
|
||||
REG(u.s.X17, 8, CONTEXT_INTEGER),
|
||||
REG(u.s.X18, 8, CONTEXT_INTEGER),
|
||||
REG(u.s.X19, 8, CONTEXT_INTEGER),
|
||||
REG(u.s.X20, 8, CONTEXT_INTEGER),
|
||||
REG(u.s.X21, 8, CONTEXT_INTEGER),
|
||||
REG(u.s.X22, 8, CONTEXT_INTEGER),
|
||||
REG(u.s.X23, 8, CONTEXT_INTEGER),
|
||||
REG(u.s.X24, 8, CONTEXT_INTEGER),
|
||||
REG(u.s.X25, 8, CONTEXT_INTEGER),
|
||||
REG(u.s.X26, 8, CONTEXT_INTEGER),
|
||||
REG(u.s.X27, 8, CONTEXT_INTEGER),
|
||||
REG(u.s.X28, 8, CONTEXT_INTEGER),
|
||||
REG(u.s.Fp, 8, CONTEXT_INTEGER),
|
||||
REG(u.s.Lr, 8, CONTEXT_INTEGER),
|
||||
REG(Sp, 8, CONTEXT_CONTROL),
|
||||
REG(Pc, 8, CONTEXT_CONTROL),
|
||||
REG(Cpsr, 4),
|
||||
REG(u.s.X0, 8),
|
||||
REG(u.s.X1, 8),
|
||||
REG(u.s.X2, 8),
|
||||
REG(u.s.X3, 8),
|
||||
REG(u.s.X4, 8),
|
||||
REG(u.s.X5, 8),
|
||||
REG(u.s.X6, 8),
|
||||
REG(u.s.X7, 8),
|
||||
REG(u.s.X8, 8),
|
||||
REG(u.s.X9, 8),
|
||||
REG(u.s.X10, 8),
|
||||
REG(u.s.X11, 8),
|
||||
REG(u.s.X12, 8),
|
||||
REG(u.s.X13, 8),
|
||||
REG(u.s.X14, 8),
|
||||
REG(u.s.X15, 8),
|
||||
REG(u.s.X16, 8),
|
||||
REG(u.s.X17, 8),
|
||||
REG(u.s.X18, 8),
|
||||
REG(u.s.X19, 8),
|
||||
REG(u.s.X20, 8),
|
||||
REG(u.s.X21, 8),
|
||||
REG(u.s.X22, 8),
|
||||
REG(u.s.X23, 8),
|
||||
REG(u.s.X24, 8),
|
||||
REG(u.s.X25, 8),
|
||||
REG(u.s.X26, 8),
|
||||
REG(u.s.X27, 8),
|
||||
REG(u.s.X28, 8),
|
||||
REG(u.s.Fp, 8),
|
||||
REG(u.s.Lr, 8),
|
||||
REG(Sp, 8),
|
||||
REG(Pc, 8),
|
||||
};
|
||||
#else
|
||||
# error Define the registers map for your CPU
|
||||
|
|
@ -553,21 +552,7 @@ static inline void cpu_register_hex_from(CONTEXT* ctx, unsigned idx, const
|
|||
|
||||
static BOOL fetch_context(struct gdb_context* gdbctx, HANDLE h, CONTEXT* ctx)
|
||||
{
|
||||
ctx->ContextFlags = CONTEXT_CONTROL
|
||||
| CONTEXT_INTEGER
|
||||
#if defined(__powerpc__) || defined(__i386__) || defined(__x86_64__)
|
||||
| CONTEXT_FLOATING_POINT
|
||||
#endif
|
||||
#ifdef CONTEXT_SEGMENTS
|
||||
| CONTEXT_SEGMENTS
|
||||
#endif
|
||||
#ifdef CONTEXT_DEBUG_REGISTERS
|
||||
| CONTEXT_DEBUG_REGISTERS
|
||||
#endif
|
||||
#ifdef CONTEXT_EXTENDED_REGISTERS
|
||||
| CONTEXT_EXTENDED_REGISTERS
|
||||
#endif
|
||||
;
|
||||
ctx->ContextFlags = CONTEXT_ALL;
|
||||
if (!GetThreadContext(h, ctx))
|
||||
{
|
||||
if (gdbctx->trace & GDBPXY_TRC_WIN32_ERROR)
|
||||
|
|
@ -1135,10 +1120,6 @@ static enum packet_return packet_reply_status(struct gdb_context* gdbctx)
|
|||
|
||||
for (i = 0; i < cpu_num_regs; i++)
|
||||
{
|
||||
ULONG flags = cpu_register_map[i].ctx_flags;
|
||||
if ((gdbctx->context.ContextFlags & flags) != flags)
|
||||
break;
|
||||
|
||||
/* FIXME: this call will also grow the buffer...
|
||||
* unneeded, but not harmful
|
||||
*/
|
||||
|
|
@ -1474,12 +1455,7 @@ static enum packet_return packet_read_registers(struct gdb_context* gdbctx)
|
|||
|
||||
packet_reply_open(gdbctx);
|
||||
for (i = 0; i < cpu_num_regs; i++)
|
||||
{
|
||||
ULONG flags = cpu_register_map[i].ctx_flags;
|
||||
if ((gdbctx->context.ContextFlags & flags) != flags)
|
||||
break;
|
||||
packet_reply_register_hex_to(gdbctx, i);
|
||||
}
|
||||
packet_reply_close(gdbctx);
|
||||
return packet_done;
|
||||
}
|
||||
|
|
@ -1501,12 +1477,8 @@ static enum packet_return packet_write_registers(struct gdb_context* gdbctx)
|
|||
|
||||
ptr = gdbctx->in_packet;
|
||||
for (i = 0; i < cpu_num_regs; i++)
|
||||
{
|
||||
ULONG flags = cpu_register_map[i].ctx_flags;
|
||||
if ((pctx->ContextFlags & flags) != flags)
|
||||
break;
|
||||
cpu_register_hex_from(pctx, i, &ptr);
|
||||
}
|
||||
|
||||
if (pctx != &gdbctx->context && !SetThreadContext(gdbctx->other_thread->handle, pctx))
|
||||
{
|
||||
if (gdbctx->trace & GDBPXY_TRC_WIN32_ERROR)
|
||||
|
|
@ -1704,12 +1676,6 @@ static enum packet_return packet_write_register(struct gdb_context* gdbctx)
|
|||
if (!fetch_context(gdbctx, gdbctx->other_thread->handle, pctx = &ctx))
|
||||
return packet_error;
|
||||
}
|
||||
if ((pctx->ContextFlags & cpu_register_map[reg].ctx_flags) != cpu_register_map[reg].ctx_flags)
|
||||
{
|
||||
if (gdbctx->trace & GDBPXY_TRC_COMMAND_ERROR)
|
||||
fprintf(stderr, "Writing reg %u is not supported on this host\n", reg);
|
||||
return packet_error;
|
||||
}
|
||||
|
||||
cpu_register_hex_from(pctx, reg, (const char**)&ptr);
|
||||
if (pctx != &gdbctx->context && !SetThreadContext(gdbctx->other_thread->handle, pctx))
|
||||
|
|
|
|||
Loading…
Reference in New Issue