winedbg: Fix parsing table for ARM disassembler.
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@ -102,12 +102,19 @@ static UINT arm_disasm_branch(UINT inst)
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return 0;
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}
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static UINT arm_disasm_branchreg(UINT inst)
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{
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dbg_printf("\n\tb%s\t%s", get_cond(inst), tbl_regs[get_nibble(inst, 0)]);
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return 0;
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}
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static UINT arm_disasm_dataprocessing(UINT inst)
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{
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short condcodes = (inst >> 20) & 0x01;
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short opcode = (inst >> 21) & 0x0f;
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short immediate = (inst >> 25) & 0x01;
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short no_op1 = (opcode & 0x0d) == 0x0d;
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short no_dst = (opcode & 0x0c) == 0x08;
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/* check for nop */
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if (get_nibble(inst, 3) == 15 /* r15 */ && condcodes == 0 &&
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@ -118,7 +125,9 @@ static UINT arm_disasm_dataprocessing(UINT inst)
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}
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dbg_printf("\n\t%s%s%s", tbl_dataops[opcode], condcodes ? "s" : "", get_cond(inst));
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dbg_printf("\t%s, ", tbl_regs[get_nibble(inst, 3)]);
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if (!no_dst) dbg_printf("\t%s, ", tbl_regs[get_nibble(inst, 3)]);
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else dbg_printf("\t");
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if (no_op1)
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{
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if (immediate)
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@ -395,9 +404,10 @@ struct inst_arm
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static const struct inst_arm tbl_arm[] = {
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{ 0x0e000000, 0x0a000000, arm_disasm_branch },
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{ 0x0e000090, 0x00000090, arm_disasm_halfwordtrans },
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{ 0x0fffff00, 0x012fff00, arm_disasm_branchreg },
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{ 0x0c000000, 0x00000000, arm_disasm_dataprocessing },
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{ 0x0c000000, 0x04000000, arm_disasm_singletrans },
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{ 0x0e000090, 0x00000090, arm_disasm_halfwordtrans },
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{ 0x0e000000, 0x08000000, arm_disasm_blocktrans },
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{ 0x0f000000, 0x0f000000, arm_disasm_swi },
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{ 0x0f000010, 0x0e000010, arm_disasm_coproctrans },
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