winedbg: Add load non-word operators to Thumb2 disassembler.
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@ -992,6 +992,68 @@ static UINT thumb2_disasm_preload(UINT inst, ADDRESS64 *addr)
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return inst;
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return inst;
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}
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}
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static UINT thumb2_disasm_ldrnonword(UINT inst, ADDRESS64 *addr)
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{
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WORD op1 = (inst >> 23) & 0x03;
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WORD hw = (inst >> 21) & 0x01;
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if (!(op1 & 0x01) && !((inst >> 6) & 0x3f) && get_nibble(inst, 4) != 15)
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{
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WORD shift = (inst >> 4) & 0x03;
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dbg_printf("\n\t%s%s\t%s, [%s, %s", op1?"ldrs":"ldr", hw?"h":"b",
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tbl_regs[get_nibble(inst, 3)], tbl_regs[get_nibble(inst, 4)],
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tbl_regs[get_nibble(inst, 0)]);
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if (shift) dbg_printf(", lsl #%u]", shift);
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else dbg_printf("]");
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return 0;
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}
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if (!(op1 & 0x01) && ((inst >> 8) & 0x0f) == 14 && get_nibble(inst, 4) != 15)
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{
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WORD offset = inst & 0xff;
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dbg_printf("\n\t%s%s\t%s, [%s", op1?"ldrs":"ldr", hw?"ht":"bt",
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tbl_regs[get_nibble(inst, 3)], tbl_regs[get_nibble(inst, 4)]);
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if (offset) dbg_printf(", #%u]", offset);
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else dbg_printf("]");
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return 0;
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}
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if (get_nibble(inst, 4) != 15)
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{
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int offset;
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dbg_printf("\n\t%s%s\t%s, [%s", (op1 & 0x02)?"ldrs":"ldr", hw?"h":"b",
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tbl_regs[get_nibble(inst, 3)], tbl_regs[get_nibble(inst, 4)]);
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if (op1 & 0x01)
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{
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dbg_printf(", #%u]", inst & 0x0fff);
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return 0;
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}
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offset = inst & 0xff;
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if (!(inst & 0x0200)) offset *= -1;
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if (!(inst & 0x0400) && (inst & 0x0100)) dbg_printf("], #%i", offset);
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else if (inst & 0x0400) dbg_printf(", #%i]%s", offset, (inst & 0x0100)?"!":"");
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else return inst;
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return 0;
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}
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if (get_nibble(inst, 4) == 15)
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{
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int offset = inst & 0x0fff;
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if (!op1) offset *= -1;
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dbg_printf("\n\t%s%s\t%s, ", (op1 & 0x02)?"ldrs":"ldr", hw?"h":"b",
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tbl_regs[get_nibble(inst, 3)]);
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db_printsym(addr->Offset + offset + 4);
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return 0;
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}
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return inst;
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}
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static UINT thumb2_disasm_coprocdat(UINT inst, ADDRESS64 *addr)
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static UINT thumb2_disasm_coprocdat(UINT inst, ADDRESS64 *addr)
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{
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{
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WORD opc2 = (inst >> 5) & 0x07;
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WORD opc2 = (inst >> 5) & 0x07;
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@ -1139,6 +1201,7 @@ static const struct inst_arm tbl_thumb32[] = {
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{ 0xff100000, 0xf8000000, thumb2_disasm_str },
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{ 0xff100000, 0xf8000000, thumb2_disasm_str },
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{ 0xff700000, 0xf8500000, thumb2_disasm_ldrword },
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{ 0xff700000, 0xf8500000, thumb2_disasm_ldrword },
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{ 0xfe70f000, 0xf810f000, thumb2_disasm_preload },
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{ 0xfe70f000, 0xf810f000, thumb2_disasm_preload },
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{ 0xfe500000, 0xf8100000, thumb2_disasm_ldrnonword },
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{ 0xef000010, 0xee000000, thumb2_disasm_coprocdat },
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{ 0xef000010, 0xee000000, thumb2_disasm_coprocdat },
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{ 0xef000010, 0xee000010, thumb2_disasm_coprocmov1 },
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{ 0xef000010, 0xee000010, thumb2_disasm_coprocmov1 },
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{ 0xefe00000, 0xec400000, thumb2_disasm_coprocmov2 },
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{ 0xefe00000, 0xec400000, thumb2_disasm_coprocmov2 },
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