winebuild: Simplify ARM64 import thunks.
Signed-off-by: Alexandre Julliard <julliard@winehq.org>
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00401d2278
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90ac46fe33
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@ -760,14 +760,11 @@ static void output_import_thunk( const char *name, const char *table, int pos )
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output( "1:\t.long %s+%u-(1b+4)\n", table, pos );
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output( "1:\t.long %s+%u-(1b+4)\n", table, pos );
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break;
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break;
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case CPU_ARM64:
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case CPU_ARM64:
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output( "\tadrp x9, %s\n", arm64_page( table ) );
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output( "\tadrp x16, %s\n", arm64_page( table ) );
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output( "\tadd x9, x9, #%s\n", arm64_pageoff( table ) );
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output( "\tadd x16, x16, #%s\n", arm64_pageoff( table ) );
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if (pos & 0xf000) output( "\tadd x9, x9, #%u\n", pos & 0xf000 );
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if (pos & ~0x7fff) output( "\tadd x16, x16, #%u\n", pos & ~0x7fff );
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if (pos & 0x0f00) output( "\tadd x9, x9, #%u\n", pos & 0x0f00 );
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output( "\tldr x16, [x16, #%u]\n", pos & 0x7fff );
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if (pos & 0x00f0) output( "\tadd x9, x9, #%u\n", pos & 0x00f0 );
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output( "\tbr x16\n" );
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if (pos & 0x000f) output( "\tadd x9, x9, #%u\n", pos & 0x000f );
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output( "\tldur x9, [x9, #0]\n" );
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output( "\tbr x9\n" );
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break;
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break;
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case CPU_POWERPC:
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case CPU_POWERPC:
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output( "\tmr %s, %s\n", ppc_reg(0), ppc_reg(31) );
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output( "\tmr %s, %s\n", ppc_reg(0), ppc_reg(31) );
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@ -1078,18 +1075,21 @@ static void output_delayed_import_thunks( const DLLSPEC *spec )
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output( "2:\t.long %s-1b\n", asm_name("__wine_spec_delay_load") );
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output( "2:\t.long %s-1b\n", asm_name("__wine_spec_delay_load") );
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break;
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break;
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case CPU_ARM64:
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case CPU_ARM64:
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output( "\tstp x29, x30, [sp,#-16]!\n" );
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output( "\tstp x29, x30, [sp,#-80]!\n" );
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output( "\tmov x29, sp\n" );
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output( "\tmov x29, sp\n" );
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output( "\tadrp x9, %s\n", arm64_page( asm_name("__wine_spec_delay_load") ) );
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output( "\tstp x0, x1, [sp,#16]\n" );
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output( "\tadd x9, x9, #%s\n", arm64_pageoff( asm_name("__wine_spec_delay_load") ) );
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output( "\tstp x2, x3, [sp,#32]\n" );
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output( "\tblr x9\n" );
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output( "\tstp x4, x5, [sp,#48]\n" );
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output( "\tmov x9, x0\n" );
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output( "\tstp x6, x7, [sp,#64]\n" );
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output( "\tldp x29, x30, [sp],#16\n" );
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output( "\tmov x0, x16\n" );
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output( "\tbl %s\n", asm_name("__wine_spec_delay_load") );
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output( "\tmov x16, x0\n" );
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output( "\tldp x0, x1, [sp,#16]\n" );
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output( "\tldp x0, x1, [sp,#16]\n" );
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output( "\tldp x2, x3, [sp,#32]\n" );
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output( "\tldp x2, x3, [sp,#32]\n" );
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output( "\tldp x4, x5, [sp,#48]\n" );
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output( "\tldp x4, x5, [sp,#48]\n" );
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output( "\tldp x6, x7, [sp],#80\n" );
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output( "\tldp x6, x7, [sp,#64]\n" );
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output( "\tbr x9\n" ); /* or "ret x9" */
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output( "\tldp x29, x30, [sp],#80\n" );
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output( "\tbr x16\n" );
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break;
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break;
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case CPU_POWERPC:
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case CPU_POWERPC:
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if (target_platform == PLATFORM_APPLE) extra_stack_storage = 56;
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if (target_platform == PLATFORM_APPLE) extra_stack_storage = 56;
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@ -1176,20 +1176,13 @@ static void output_delayed_import_thunks( const DLLSPEC *spec )
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break;
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break;
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}
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}
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case CPU_ARM64:
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case CPU_ARM64:
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output( "\tstp x6, x7, [sp,#-80]!\n" );
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if (idx)
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output( "\tstp x4, x5, [sp,#48]\n" );
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{
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output( "\tstp x2, x3, [sp,#32]\n" );
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output( "\tmov x16, #0x%x\n", idx << 16 );
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output( "\tstp x0, x1, [sp,#16]\n" );
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if (j) output( "\tmovk x16, #0x%x\n", j );
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output( "\tmov x0, #%d\n", idx );
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}
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output( "\tmov x1, #16384\n" );
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else output( "\tmov x16, #0x%x\n", j );
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output( "\tmul x1, x0, x1\n" );
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output( "\tb %s\n", asm_name("__wine_delay_load_asm") );
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output( "\tmov x0, x1\n" );
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output( "\tmov x1, #4\n" );
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output( "\tmul x1, x0, x1\n" );
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output( "\tmov x0, x1\n" );
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output( "\tadd x0, x0, #%d\n", j );
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output( "\tadr x9, %s\n", asm_name("__wine_delay_load_asm") );
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output( "\tbr x9\n" );
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break;
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break;
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case CPU_POWERPC:
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case CPU_POWERPC:
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switch(target_platform)
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switch(target_platform)
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@ -1378,9 +1371,7 @@ void output_stubs( DLLSPEC *spec )
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}
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}
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else
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else
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output( "\tmov x1, %u\n", odp->ordinal );
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output( "\tmov x1, %u\n", odp->ordinal );
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output( "\tadrp x2, %s\n", arm64_page( asm_name("__wine_spec_unimplemented_stub") ) );
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output( "\tbl %s\n", asm_name("__wine_spec_unimplemented_stub") );
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output( "\tadd x2, x2, #%s\n", arm64_pageoff( asm_name("__wine_spec_unimplemented_stub") ) );
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output( "\tblr x2\n" );
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break;
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break;
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default:
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default:
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assert(0);
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assert(0);
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