d3dx9: Add <= ps_1_3 instruction parsing to the shader assembler.
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383a7fe3b1
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@ -165,9 +165,26 @@ mova {return INSTR_MOVA; }
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cnd {return INSTR_CND; }
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cmp {return INSTR_CMP; }
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dp2add {return INSTR_DP2ADD; }
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texcoord {return INSTR_TEXCOORD; }
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texcrd {return INSTR_TEXCRD; }
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texkill {return INSTR_TEXKILL; }
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tex {return INSTR_TEX; }
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texld {return INSTR_TEXLD; }
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texbem {return INSTR_TEXBEM; }
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texbeml {return INSTR_TEXBEML; }
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texreg2ar {return INSTR_TEXREG2AR; }
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texreg2gb {return INSTR_TEXREG2GB; }
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texreg2rgb {return INSTR_TEXREG2RGB; }
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texm3x2pad {return INSTR_TEXM3x2PAD; }
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texm3x2tex {return INSTR_TEXM3x2TEX; }
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texm3x3pad {return INSTR_TEXM3x3PAD; }
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texm3x3spec {return INSTR_TEXM3x3SPEC; }
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texm3x3vspec {return INSTR_TEXM3x3VSPEC; }
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texm3x3tex {return INSTR_TEXM3x3TEX; }
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texdp3tex {return INSTR_TEXDP3TEX; }
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texm3x2depth {return INSTR_TEXM3x2DEPTH; }
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texdp3 {return INSTR_TEXDP3; }
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texm3x3 {return INSTR_TEXM3x3; }
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texdepth {return INSTR_TEXDEPTH; }
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bem {return INSTR_BEM; }
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dsx {return INSTR_DSX; }
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@ -151,9 +151,26 @@ void set_rel_reg(struct shader_reg *reg, struct rel_reg *rel) {
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%token INSTR_CND
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%token INSTR_CMP
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%token INSTR_DP2ADD
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%token INSTR_TEXCOORD
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%token INSTR_TEXCRD
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%token INSTR_TEXKILL
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%token INSTR_TEX
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%token INSTR_TEXLD
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%token INSTR_TEXBEM
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%token INSTR_TEXBEML
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%token INSTR_TEXREG2AR
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%token INSTR_TEXREG2GB
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%token INSTR_TEXREG2RGB
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%token INSTR_TEXM3x2PAD
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%token INSTR_TEXM3x2TEX
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%token INSTR_TEXM3x3PAD
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%token INSTR_TEXM3x3SPEC
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%token INSTR_TEXM3x3VSPEC
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%token INSTR_TEXM3x3TEX
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%token INSTR_TEXDP3TEX
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%token INSTR_TEXM3x2DEPTH
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%token INSTR_TEXDP3
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%token INSTR_TEXM3x3
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%token INSTR_TEXDEPTH
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%token INSTR_BEM
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%token INSTR_DSX
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@ -810,6 +827,11 @@ instruction: INSTR_ADD omods dreg ',' sregs
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TRACE("DP2ADD\n");
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asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_DP2ADD, $2.mod, $2.shift, 0, &$3, &$5, 3);
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}
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| INSTR_TEXCOORD omods dreg
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{
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TRACE("TEXCOORD\n");
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asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_TEXCOORD, $2.mod, $2.shift, 0, &$3, 0, 0);
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}
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| INSTR_TEXCRD omods dreg ',' sregs
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{
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TRACE("TEXCRD\n");
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@ -821,6 +843,11 @@ instruction: INSTR_ADD omods dreg ',' sregs
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TRACE("TEXKILL\n");
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asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_TEXKILL, 0, 0, 0, &$2, 0, 0);
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}
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| INSTR_TEX omods dreg
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{
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TRACE("TEX\n");
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asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_TEX, $2.mod, $2.shift, 0, &$3, 0, 0);
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}
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| INSTR_TEXDEPTH omods dreg
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{
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TRACE("TEXDEPTH\n");
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@ -847,6 +874,81 @@ instruction: INSTR_ADD omods dreg ',' sregs
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TRACE("TEXLDB\n");
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asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_TEXLDB, $2.mod, $2.shift, 0, &$3, &$5, 2);
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}
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| INSTR_TEXBEM omods dreg ',' sregs
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{
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TRACE("TEXBEM\n");
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asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_TEXBEM, $2.mod, $2.shift, 0, &$3, &$5, 1);
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}
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| INSTR_TEXBEML omods dreg ',' sregs
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{
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TRACE("TEXBEML\n");
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asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_TEXBEML, $2.mod, $2.shift, 0, &$3, &$5, 1);
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}
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| INSTR_TEXREG2AR omods dreg ',' sregs
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{
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TRACE("TEXREG2AR\n");
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asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_TEXREG2AR, $2.mod, $2.shift, 0, &$3, &$5, 1);
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}
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| INSTR_TEXREG2GB omods dreg ',' sregs
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{
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TRACE("TEXREG2GB\n");
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asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_TEXREG2GB, $2.mod, $2.shift, 0, &$3, &$5, 1);
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}
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| INSTR_TEXREG2RGB omods dreg ',' sregs
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{
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TRACE("TEXREG2RGB\n");
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asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_TEXREG2RGB, $2.mod, $2.shift, 0, &$3, &$5, 1);
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}
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| INSTR_TEXM3x2PAD omods dreg ',' sregs
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{
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TRACE("TEXM3x2PAD\n");
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asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_TEXM3x2PAD, $2.mod, $2.shift, 0, &$3, &$5, 1);
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}
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| INSTR_TEXM3x3PAD omods dreg ',' sregs
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{
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TRACE("INSTR_TEXM3x3PAD\n");
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asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_TEXM3x3PAD, $2.mod, $2.shift, 0, &$3, &$5, 1);
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}
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| INSTR_TEXM3x3SPEC omods dreg ',' sregs
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{
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TRACE("TEXM3x3SPEC\n");
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asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_TEXM3x3SPEC, $2.mod, $2.shift, 0, &$3, &$5, 2);
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}
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| INSTR_TEXM3x3VSPEC omods dreg ',' sregs
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{
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TRACE("TEXM3x3VSPEC\n");
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asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_TEXM3x3VSPEC, $2.mod, $2.shift, 0, &$3, &$5, 1);
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}
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| INSTR_TEXM3x3TEX omods dreg ',' sregs
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{
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TRACE("TEXM3x3TEX\n");
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asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_TEXM3x3TEX, $2.mod, $2.shift, 0, &$3, &$5, 1);
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}
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| INSTR_TEXDP3TEX omods dreg ',' sregs
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{
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TRACE("TEXDP3TEX\n");
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asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_TEXDP3TEX, $2.mod, $2.shift, 0, &$3, &$5, 1);
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}
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| INSTR_TEXM3x2DEPTH omods dreg ',' sregs
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{
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TRACE("TEXM3x2DEPTH\n");
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asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_TEXM3x2DEPTH, $2.mod, $2.shift, 0, &$3, &$5, 1);
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}
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| INSTR_TEXM3x2TEX omods dreg ',' sregs
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{
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TRACE("TEXM3x2TEX\n");
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asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_TEXM3x2TEX, $2.mod, $2.shift, 0, &$3, &$5, 1);
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}
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| INSTR_TEXDP3 omods dreg ',' sregs
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{
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TRACE("TEXDP3\n");
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asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_TEXDP3, $2.mod, $2.shift, 0, &$3, &$5, 1);
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}
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| INSTR_TEXM3x3 omods dreg ',' sregs
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{
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TRACE("TEXM3x3\n");
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asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_TEXM3x3, $2.mod, $2.shift, 0, &$3, &$5, 1);
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}
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| INSTR_BEM omods dreg ',' sregs
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{
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TRACE("BEM\n");
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@ -204,10 +204,25 @@ DWORD d3d9_opcode(DWORD bwriter_opcode) {
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case BWRITERSIO_TEXCOORD: return D3DSIO_TEXCOORD;
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case BWRITERSIO_TEXKILL: return D3DSIO_TEXKILL;
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case BWRITERSIO_TEX: return D3DSIO_TEX;
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case BWRITERSIO_TEXBEM: return D3DSIO_TEXBEM;
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case BWRITERSIO_TEXBEML: return D3DSIO_TEXBEML;
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case BWRITERSIO_TEXREG2AR: return D3DSIO_TEXREG2AR;
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case BWRITERSIO_TEXREG2GB: return D3DSIO_TEXREG2GB;
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case BWRITERSIO_TEXM3x2PAD: return D3DSIO_TEXM3x2PAD;
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case BWRITERSIO_TEXM3x2TEX: return D3DSIO_TEXM3x2TEX;
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case BWRITERSIO_TEXM3x3PAD: return D3DSIO_TEXM3x3PAD;
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case BWRITERSIO_TEXM3x3TEX: return D3DSIO_TEXM3x3TEX;
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case BWRITERSIO_TEXM3x3SPEC: return D3DSIO_TEXM3x3SPEC;
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case BWRITERSIO_TEXM3x3VSPEC:return D3DSIO_TEXM3x3VSPEC;
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case BWRITERSIO_EXPP: return D3DSIO_EXPP;
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case BWRITERSIO_LOGP: return D3DSIO_LOGP;
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case BWRITERSIO_CND: return D3DSIO_CND;
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case BWRITERSIO_DEF: return D3DSIO_DEF;
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case BWRITERSIO_TEXREG2RGB: return D3DSIO_TEXREG2RGB;
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case BWRITERSIO_TEXDP3TEX: return D3DSIO_TEXDP3TEX;
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case BWRITERSIO_TEXM3x2DEPTH:return D3DSIO_TEXM3x2DEPTH;
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case BWRITERSIO_TEXDP3: return D3DSIO_TEXDP3;
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case BWRITERSIO_TEXM3x3: return D3DSIO_TEXM3x3;
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case BWRITERSIO_TEXDEPTH: return D3DSIO_TEXDEPTH;
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case BWRITERSIO_CMP: return D3DSIO_CMP;
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case BWRITERSIO_BEM: return D3DSIO_BEM;
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@ -553,10 +568,25 @@ const char *debug_print_opcode(DWORD opcode) {
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case BWRITERSIO_TEXCOORD: return "texcoord";
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case BWRITERSIO_TEXKILL: return "texkill";
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case BWRITERSIO_TEX: return "tex";
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case BWRITERSIO_TEXBEM: return "texbem";
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case BWRITERSIO_TEXBEML: return "texbeml";
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case BWRITERSIO_TEXREG2AR: return "texreg2ar";
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case BWRITERSIO_TEXREG2GB: return "texreg2gb";
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case BWRITERSIO_TEXM3x2PAD: return "texm3x2pad";
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case BWRITERSIO_TEXM3x2TEX: return "texm3x2tex";
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case BWRITERSIO_TEXM3x3PAD: return "texm3x3pad";
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case BWRITERSIO_TEXM3x3TEX: return "texm3x3tex";
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case BWRITERSIO_TEXM3x3SPEC: return "texm3x3vspec";
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case BWRITERSIO_TEXM3x3VSPEC: return "texm3x3vspec";
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case BWRITERSIO_EXPP: return "expp";
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case BWRITERSIO_LOGP: return "logp";
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case BWRITERSIO_CND: return "cnd";
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case BWRITERSIO_DEF: return "def";
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case BWRITERSIO_TEXREG2RGB: return "texreg2rgb";
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case BWRITERSIO_TEXDP3TEX: return "texdp3tex";
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case BWRITERSIO_TEXM3x2DEPTH: return "texm3x2depth";
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case BWRITERSIO_TEXDP3: return "texdp3";
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case BWRITERSIO_TEXM3x3: return "texm3x3";
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case BWRITERSIO_TEXDEPTH: return "texdepth";
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case BWRITERSIO_CMP: return "cmp";
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case BWRITERSIO_BEM: return "bem";
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@ -480,10 +480,25 @@ typedef enum _BWRITERSHADER_INSTRUCTION_OPCODE_TYPE {
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BWRITERSIO_TEXCOORD,
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BWRITERSIO_TEXKILL,
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BWRITERSIO_TEX,
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BWRITERSIO_TEXBEM,
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BWRITERSIO_TEXBEML,
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BWRITERSIO_TEXREG2AR,
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BWRITERSIO_TEXREG2GB,
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BWRITERSIO_TEXM3x2PAD,
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BWRITERSIO_TEXM3x2TEX,
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BWRITERSIO_TEXM3x3PAD,
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BWRITERSIO_TEXM3x3TEX,
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BWRITERSIO_TEXM3x3SPEC,
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BWRITERSIO_TEXM3x3VSPEC,
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BWRITERSIO_EXPP,
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BWRITERSIO_LOGP,
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BWRITERSIO_CND,
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BWRITERSIO_DEF,
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BWRITERSIO_TEXREG2RGB,
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BWRITERSIO_TEXDP3TEX,
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BWRITERSIO_TEXM3x2DEPTH,
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BWRITERSIO_TEXDP3,
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BWRITERSIO_TEXM3x3,
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BWRITERSIO_TEXDEPTH,
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BWRITERSIO_CMP,
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BWRITERSIO_BEM,
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