ntdll: Split up feature detection by architecture.
This commit is contained in:
James Eder
Alexandre Julliard
parent
0d5f301352
commit
7978a38f24
443
dlls/ntdll/nt.c
443
dlls/ntdll/nt.c
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@ -811,6 +811,14 @@ NTSTATUS WINAPI NtSetIntervalProfile(
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static SYSTEM_CPU_INFORMATION cached_sci;
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/*******************************************************************************
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* Architecture specific feature detection for CPUs
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*
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* This a set of mutually exclusive #if define()s each providing its own get_cpuinfo() to be called
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* from fill_cpu_info();
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*/
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#if defined(__i386__) || defined(__x86_64__)
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#define AUTH 0x68747541 /* "Auth" */
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#define ENTI 0x69746e65 /* "enti" */
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#define CAMD 0x444d4163 /* "cAMD" */
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@ -913,6 +921,12 @@ static inline void get_cpuinfo(SYSTEM_CPU_INFORMATION* info)
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{
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unsigned int regs[4], regs2[4];
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#if defined(__i386__)
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info->Architecture = PROCESSOR_ARCHITECTURE_INTEL;
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#elif defined(__x86_64__)
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info->Architecture = PROCESSOR_ARCHITECTURE_AMD64;
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#endif
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/* We're at least a 386 */
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info->FeatureSet = CPU_FEATURE_VME | CPU_FEATURE_X86 | CPU_FEATURE_PGE;
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info->Level = 3;
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@ -1002,6 +1016,102 @@ static inline void get_cpuinfo(SYSTEM_CPU_INFORMATION* info)
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}
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}
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#elif defined(__powerpc__) || defined(__ppc__)
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static inline void get_cpuinfo(SYSTEM_CPU_INFORMATION* info)
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{
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#ifdef __APPLE__
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size_t valSize;
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int value;
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valSize = sizeof(value);
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if (sysctlbyname("hw.optional.floatingpoint", &value, &valSize, NULL, 0) == 0)
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user_shared_data->ProcessorFeatures[PF_FLOATING_POINT_EMULATED] = !value;
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valSize = sizeof(value);
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if (sysctlbyname("hw.cpusubtype", &value, &valSize, NULL, 0) == 0)
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{
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switch (value)
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{
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case CPU_SUBTYPE_POWERPC_601:
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case CPU_SUBTYPE_POWERPC_602: info->Level = 1; break;
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case CPU_SUBTYPE_POWERPC_603: info->Level = 3; break;
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case CPU_SUBTYPE_POWERPC_603e:
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case CPU_SUBTYPE_POWERPC_603ev: info->Level = 6; break;
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case CPU_SUBTYPE_POWERPC_604: info->Level = 4; break;
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case CPU_SUBTYPE_POWERPC_604e: info->Level = 9; break;
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case CPU_SUBTYPE_POWERPC_620: info->Level = 20; break;
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case CPU_SUBTYPE_POWERPC_750: /* G3/G4 derive from 603 so ... */
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case CPU_SUBTYPE_POWERPC_7400:
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case CPU_SUBTYPE_POWERPC_7450: info->Level = 6; break;
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case CPU_SUBTYPE_POWERPC_970: info->Level = 9;
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/* :o) user_shared_data->ProcessorFeatures[PF_ALTIVEC_INSTRUCTIONS_AVAILABLE] ;-) */
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break;
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default: break;
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}
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}
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#else
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FIXME("CPU Feature detection not implemented.\n");
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#endif
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info->Architecture = PROCESSOR_ARCHITECTURE_PPC;
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}
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#elif defined(__arm__)
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static inline void get_cpuinfo(SYSTEM_CPU_INFORMATION* info)
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{
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#ifdef linux
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char line[512];
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char *s, *value;
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FILE *f = fopen("/proc/cpuinfo", "r");
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if (f)
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{
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while (fgets(line, sizeof(line), f) != NULL)
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{
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/* NOTE: the ':' is the only character we can rely on */
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if (!(value = strchr(line,':')))
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continue;
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/* terminate the valuename */
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s = value - 1;
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while ((s >= line) && isspace(*s)) s--;
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*(s + 1) = '\0';
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/* and strip leading spaces from value */
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value += 1;
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while (isspace(*value)) value++;
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if ((s = strchr(value,'\n')))
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*s='\0';
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if (!strcasecmp(line, "CPU architecture"))
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{
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if (isdigit(value[0]))
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info->Level = atoi(value);
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continue;
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}
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if (!strcasecmp(line, "features"))
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{
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if (strstr(value, "vfpv3"))
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user_shared_data->ProcessorFeatures[PF_ARM_VFP_32_REGISTERS_AVAILABLE] = TRUE;
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if (strstr(value, "neon"))
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user_shared_data->ProcessorFeatures[PF_ARM_NEON_INSTRUCTIONS_AVAILABLE] = TRUE;
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continue;
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}
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}
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fclose(f);
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}
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#else
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FIXME("CPU Feature detection not implemented.\n");
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#endif
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info->Architecture = PROCESSOR_ARCHITECTURE_ARM;
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}
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#elif defined(__sparc__)
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static inline void get_cpuinfo(SYSTEM_CPU_INFORMATION* info)
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{
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info->Architecture = PROCESSOR_ARCHITECTURE_SPARC;
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}
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#endif /* End architecture specific feature detection for CPUs */
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/******************************************************************
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* fill_cpu_info
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*
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@ -1038,339 +1148,8 @@ void fill_cpu_info(void)
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NtCurrentTeb()->Peb->NumberOfProcessors = num;
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memset(&cached_sci, 0, sizeof(cached_sci));
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/* choose sensible defaults ...
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* FIXME: perhaps overridable with precompiler flags?
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*/
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#ifdef __i386__
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cached_sci.Architecture = PROCESSOR_ARCHITECTURE_INTEL;
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cached_sci.Level = 5; /* 586 */
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#elif defined(__x86_64__)
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cached_sci.Architecture = PROCESSOR_ARCHITECTURE_AMD64;
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#elif defined(__powerpc__)
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cached_sci.Architecture = PROCESSOR_ARCHITECTURE_PPC;
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#elif defined(__arm__)
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cached_sci.Architecture = PROCESSOR_ARCHITECTURE_ARM;
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#elif defined(__sparc__)
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cached_sci.Architecture = PROCESSOR_ARCHITECTURE_SPARC;
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#else
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#error Unknown CPU
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#endif
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cached_sci.Revision = 0;
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cached_sci.Reserved = 0;
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cached_sci.FeatureSet = 0x1fff;
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get_cpuinfo(&cached_sci);
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/* Hmm, reasonable processor feature defaults? */
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#ifdef linux
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{
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char line[200];
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FILE *f = fopen ("/proc/cpuinfo", "r");
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if (!f)
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return;
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while (fgets(line,200,f) != NULL)
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{
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char *s,*value;
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/* NOTE: the ':' is the only character we can rely on */
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if (!(value = strchr(line,':')))
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continue;
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/* terminate the valuename */
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s = value - 1;
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while ((s >= line) && ((*s == ' ') || (*s == '\t'))) s--;
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*(s + 1) = '\0';
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/* and strip leading spaces from value */
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value += 1;
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while (*value==' ') value++;
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if ((s = strchr(value,'\n')))
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*s='\0';
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if (!strcasecmp(line, "model"))
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{
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/* First part of Revision */
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int x;
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if (sscanf(value, "%d",&x))
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cached_sci.Revision = cached_sci.Revision | (x << 8);
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continue;
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}
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/* 2.1 and ARM method */
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if (!strcasecmp(line, "cpu family") || !strcasecmp(line, "CPU architecture"))
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{
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if (isdigit(value[0]))
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{
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cached_sci.Level = atoi(value);
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}
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continue;
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}
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/* old 2.0 method */
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if (!strcasecmp(line, "cpu"))
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{
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if (isdigit(value[0]) && value[1] == '8' && value[2] == '6' && value[3] == 0)
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{
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switch (cached_sci.Level = value[0] - '0')
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{
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case 3:
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case 4:
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case 5:
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case 6:
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break;
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default:
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FIXME("unknown Linux 2.0 cpu family '%s', please report ! (-> setting to 386)\n", value);
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cached_sci.Level = 3;
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break;
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}
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}
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continue;
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}
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if (!strcasecmp(line, "stepping"))
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{
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/* Second part of Revision */
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int x;
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if (sscanf(value, "%d",&x))
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cached_sci.Revision = cached_sci.Revision | x;
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continue;
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}
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if (!strcasecmp(line, "fdiv_bug"))
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{
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if (!strncasecmp(value, "yes",3))
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user_shared_data->ProcessorFeatures[PF_FLOATING_POINT_PRECISION_ERRATA] = TRUE;
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continue;
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}
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if (!strcasecmp(line, "fpu"))
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{
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if (!strncasecmp(value, "no",2))
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user_shared_data->ProcessorFeatures[PF_FLOATING_POINT_EMULATED] = TRUE;
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continue;
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}
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if (!strcasecmp(line, "flags") || !strcasecmp(line, "features"))
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{
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if (strstr(value, "cx8"))
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user_shared_data->ProcessorFeatures[PF_COMPARE_EXCHANGE_DOUBLE] = TRUE;
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if (strstr(value, "cx16"))
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user_shared_data->ProcessorFeatures[PF_COMPARE_EXCHANGE128] = TRUE;
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if (strstr(value, "mmx"))
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user_shared_data->ProcessorFeatures[PF_MMX_INSTRUCTIONS_AVAILABLE] = TRUE;
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if (strstr(value, "nx"))
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user_shared_data->ProcessorFeatures[PF_NX_ENABLED] = TRUE;
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if (strstr(value, "tsc"))
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user_shared_data->ProcessorFeatures[PF_RDTSC_INSTRUCTION_AVAILABLE] = TRUE;
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if (strstr(value, "3dnow"))
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{
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user_shared_data->ProcessorFeatures[PF_3DNOW_INSTRUCTIONS_AVAILABLE] = TRUE;
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cached_sci.FeatureSet |= CPU_FEATURE_3DNOW;
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}
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/* This will also catch sse2, but we have sse itself
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* if we have sse2, so no problem */
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if (strstr(value, "sse"))
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{
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user_shared_data->ProcessorFeatures[PF_XMMI_INSTRUCTIONS_AVAILABLE] = TRUE;
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cached_sci.FeatureSet |= CPU_FEATURE_SSE;
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}
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if (strstr(value, "sse2"))
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{
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user_shared_data->ProcessorFeatures[PF_XMMI64_INSTRUCTIONS_AVAILABLE] = TRUE;
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cached_sci.FeatureSet |= CPU_FEATURE_SSE2;
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}
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if (strstr(value, "pni"))
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user_shared_data->ProcessorFeatures[PF_SSE3_INSTRUCTIONS_AVAILABLE] = TRUE;
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if (strstr(value, "pae"))
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user_shared_data->ProcessorFeatures[PF_PAE_ENABLED] = TRUE;
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if (strstr(value, "ht"))
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cached_sci.FeatureSet |= CPU_FEATURE_HTT;
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continue;
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}
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}
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fclose(f);
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}
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#elif defined (__NetBSD__)
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{
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int mib[2];
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int value;
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size_t val_len;
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char model[256];
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char *cpuclass;
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FILE *f = fopen("/var/run/dmesg.boot", "r");
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/* first deduce as much as possible from the sysctls */
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mib[0] = CTL_MACHDEP;
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#ifdef CPU_FPU_PRESENT
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mib[1] = CPU_FPU_PRESENT;
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val_len = sizeof(value);
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if (sysctl(mib, 2, &value, &val_len, NULL, 0) >= 0)
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user_shared_data->ProcessorFeatures[PF_FLOATING_POINT_EMULATED] = !value;
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#endif
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#ifdef CPU_SSE
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mib[1] = CPU_SSE; /* this should imply MMX */
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val_len = sizeof(value);
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if (sysctl(mib, 2, &value, &val_len, NULL, 0) >= 0)
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if (value) user_shared_data->ProcessorFeatures[PF_MMX_INSTRUCTIONS_AVAILABLE] = TRUE;
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#endif
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#ifdef CPU_SSE2
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mib[1] = CPU_SSE2; /* this should imply MMX */
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val_len = sizeof(value);
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if (sysctl(mib, 2, &value, &val_len, NULL, 0) >= 0)
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if (value) user_shared_data->ProcessorFeatures[PF_MMX_INSTRUCTIONS_AVAILABLE] = TRUE;
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#endif
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mib[0] = CTL_HW;
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mib[1] = HW_MODEL;
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val_len = sizeof(model)-1;
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if (sysctl(mib, 2, model, &val_len, NULL, 0) >= 0)
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{
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model[val_len] = '\0'; /* just in case */
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cpuclass = strstr(model, "-class");
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if (cpuclass != NULL) {
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while(cpuclass > model && cpuclass[0] != '(') cpuclass--;
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if (!strncmp(cpuclass+1, "386", 3))
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{
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cached_sci.Level= 3;
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}
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if (!strncmp(cpuclass+1, "486", 3))
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{
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cached_sci.Level= 4;
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}
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if (!strncmp(cpuclass+1, "586", 3))
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{
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cached_sci.Level= 5;
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}
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if (!strncmp(cpuclass+1, "686", 3))
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{
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cached_sci.Level= 6;
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/* this should imply MMX */
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user_shared_data->ProcessorFeatures[PF_MMX_INSTRUCTIONS_AVAILABLE] = TRUE;
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}
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}
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}
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/* it may be worth reading from /var/run/dmesg.boot for
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additional information such as CX8, MMX and TSC
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(however this information should be considered less
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reliable than that from the sysctl calls) */
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if (f != NULL)
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{
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while (fgets(model, 255, f) != NULL)
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{
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int cpu, features;
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if (sscanf(model, "cpu%d: features %x<", &cpu, &features) == 2)
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{
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/* we could scan the string but it is easier
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to test the bits directly */
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if (features & 0x1)
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user_shared_data->ProcessorFeatures[PF_FLOATING_POINT_EMULATED] = TRUE;
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if (features & 0x10)
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user_shared_data->ProcessorFeatures[PF_RDTSC_INSTRUCTION_AVAILABLE] = TRUE;
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if (features & 0x100)
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user_shared_data->ProcessorFeatures[PF_COMPARE_EXCHANGE_DOUBLE] = TRUE;
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if (features & 0x800000)
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user_shared_data->ProcessorFeatures[PF_MMX_INSTRUCTIONS_AVAILABLE] = TRUE;
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break;
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}
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}
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fclose(f);
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}
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}
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#elif defined(__FreeBSD__) || defined (__FreeBSD_kernel__) || defined(__DragonFly__)
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{
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get_cpuinfo( &cached_sci );
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/* Check for OS support of SSE -- Is this used, and should it be sse1 or sse2? */
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/*len = sizeof(num);
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ret = sysctlbyname("hw.instruction_sse", &num, &len, NULL, 0);
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if (!ret)
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user_shared_data->ProcessorFeatures[PF_XMMI_INSTRUCTIONS_AVAILABLE] = num;*/
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}
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#elif defined(__sun)
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{
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get_cpuinfo( &cached_sci );
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}
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#elif defined (__APPLE__)
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{
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size_t valSize;
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int value;
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int cputype;
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char buffer[1024];
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valSize = sizeof(int);
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if (sysctlbyname ("hw.optional.floatingpoint", &value, &valSize, NULL, 0) == 0)
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{
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if (value)
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user_shared_data->ProcessorFeatures[PF_FLOATING_POINT_EMULATED] = FALSE;
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else
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user_shared_data->ProcessorFeatures[PF_FLOATING_POINT_EMULATED] = TRUE;
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}
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valSize = sizeof(int);
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if (sysctlbyname ("hw.cputype", &cputype, &valSize, NULL, 0) == 0)
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{
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switch (cputype)
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{
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case CPU_TYPE_POWERPC:
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cached_sci.Architecture = PROCESSOR_ARCHITECTURE_PPC;
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valSize = sizeof(int);
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if (sysctlbyname ("hw.cpusubtype", &value, &valSize, NULL, 0) == 0)
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{
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switch (value)
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{
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case CPU_SUBTYPE_POWERPC_601:
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case CPU_SUBTYPE_POWERPC_602: cached_sci.Level = 1; break;
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case CPU_SUBTYPE_POWERPC_603: cached_sci.Level = 3; break;
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case CPU_SUBTYPE_POWERPC_603e:
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case CPU_SUBTYPE_POWERPC_603ev: cached_sci.Level = 6; break;
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case CPU_SUBTYPE_POWERPC_604: cached_sci.Level = 4; break;
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case CPU_SUBTYPE_POWERPC_604e: cached_sci.Level = 9; break;
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case CPU_SUBTYPE_POWERPC_620: cached_sci.Level = 20; break;
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case CPU_SUBTYPE_POWERPC_750: /* G3/G4 derive from 603 so ... */
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case CPU_SUBTYPE_POWERPC_7400:
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case CPU_SUBTYPE_POWERPC_7450: cached_sci.Level = 6; break;
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case CPU_SUBTYPE_POWERPC_970: cached_sci.Level = 9;
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/* :o) user_shared_data->ProcessorFeatures[PF_ALTIVEC_INSTRUCTIONS_AVAILABLE] ;-) */
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break;
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default: break;
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}
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}
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break; /* CPU_TYPE_POWERPC */
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case CPU_TYPE_I386:
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cached_sci.Architecture = PROCESSOR_ARCHITECTURE_INTEL;
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valSize = sizeof(int);
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if (sysctlbyname ("machdep.cpu.family", &value, &valSize, NULL, 0) == 0)
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{
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cached_sci.Level = value;
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}
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valSize = sizeof(int);
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if (sysctlbyname ("machdep.cpu.model", &value, &valSize, NULL, 0) == 0)
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cached_sci.Revision = (value << 8);
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valSize = sizeof(int);
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||||
if (sysctlbyname ("machdep.cpu.stepping", &value, &valSize, NULL, 0) == 0)
|
||||
cached_sci.Revision |= value;
|
||||
valSize = sizeof(buffer);
|
||||
if (sysctlbyname ("machdep.cpu.features", buffer, &valSize, NULL, 0) == 0)
|
||||
{
|
||||
if (!valSize) FIXME("Buffer not large enough, please increase\n");
|
||||
if (strstr(buffer, "CX8")) user_shared_data->ProcessorFeatures[PF_COMPARE_EXCHANGE_DOUBLE] = TRUE;
|
||||
if (strstr(buffer, "CX16")) user_shared_data->ProcessorFeatures[PF_COMPARE_EXCHANGE128] = TRUE;
|
||||
if (strstr(buffer, "MMX")) user_shared_data->ProcessorFeatures[PF_MMX_INSTRUCTIONS_AVAILABLE] = TRUE;
|
||||
if (strstr(buffer, "TSC")) user_shared_data->ProcessorFeatures[PF_RDTSC_INSTRUCTION_AVAILABLE] = TRUE;
|
||||
if (strstr(buffer, "3DNOW")) user_shared_data->ProcessorFeatures[PF_3DNOW_INSTRUCTIONS_AVAILABLE] = TRUE;
|
||||
if (strstr(buffer, "SSE")) user_shared_data->ProcessorFeatures[PF_XMMI_INSTRUCTIONS_AVAILABLE] = TRUE;
|
||||
if (strstr(buffer, "SSE2")) user_shared_data->ProcessorFeatures[PF_XMMI64_INSTRUCTIONS_AVAILABLE] = TRUE;
|
||||
if (strstr(buffer, "SSE3")) user_shared_data->ProcessorFeatures[PF_SSE3_INSTRUCTIONS_AVAILABLE] = TRUE;
|
||||
if (strstr(buffer, "PAE")) user_shared_data->ProcessorFeatures[PF_PAE_ENABLED] = TRUE;
|
||||
if (strstr(buffer, "HTT")) cached_sci.FeatureSet |= CPU_FEATURE_HTT;
|
||||
}
|
||||
break; /* CPU_TYPE_I386 */
|
||||
default: break;
|
||||
} /* switch (cputype) */
|
||||
}
|
||||
}
|
||||
#else
|
||||
FIXME("not yet supported on this system\n");
|
||||
#endif
|
||||
TRACE("<- CPU arch %d, level %d, rev %d, features 0x%x\n",
|
||||
cached_sci.Architecture, cached_sci.Level, cached_sci.Revision, cached_sci.FeatureSet);
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue