winedbg: Add special register processing operators to Thumb2 disassembler.
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1e1e181b2e
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@ -92,6 +92,11 @@ static char const tbl_width_t2[][2] = {
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"b", "h", "", "?"
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};
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static char const tbl_special_regs_t2[][12] = {
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"apsr", "iapsr", "eapsr", "xpsr", "rsvd", "ipsr", "epsr", "iepsr", "msp", "psp", "rsvd", "rsvd",
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"rsvd", "rsvd", "rsvd", "rsvd", "primask", "basepri", "basepri_max", "faultmask", "control"
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};
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static UINT db_get_inst(void* addr, int size)
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{
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UINT result = 0;
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@ -661,6 +666,26 @@ static UINT thumb2_disasm_branch(UINT inst, ADDRESS64 *addr)
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return 0;
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}
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static UINT thumb2_disasm_srtrans(UINT inst, ADDRESS64 *addr)
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{
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UINT fromsr = (inst >> 21) & 0x03;
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UINT sysreg = inst & 0xff;
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if (fromsr == 3 && get_nibble(inst,4) == 0x0f && sysreg <= 20)
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{
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dbg_printf("\n\tmrs\t%s, %s", tbl_regs[get_nibble(inst, 2)], tbl_special_regs_t2[sysreg]);
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return 0;
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}
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if (fromsr == 0 && sysreg <= 20)
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{
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dbg_printf("\n\tmsr\t%s, %s", tbl_special_regs_t2[sysreg], tbl_regs[get_nibble(inst, 4)]);
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return 0;
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}
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return inst;
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}
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static UINT thumb2_disasm_misc(UINT inst, ADDRESS64 *addr)
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{
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WORD op1 = (inst >> 20) & 0x03;
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@ -965,6 +990,7 @@ static const struct inst_thumb16 tbl_thumb16[] = {
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static const struct inst_arm tbl_thumb32[] = {
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{ 0xf800f000, 0xf0008000, thumb2_disasm_branch },
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{ 0xff90f000, 0xf3808000, thumb2_disasm_srtrans },
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{ 0xffc0f0c0, 0xfa80f080, thumb2_disasm_misc },
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{ 0xff80f000, 0xfa00f000, thumb2_disasm_dataprocessingreg },
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{ 0xff8000c0, 0xfb000000, thumb2_disasm_mul },
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