ntdll: Report newer vector processor features on x86 / x64.
Signed-off-by: Paul Gofman <pgofman@codeweavers.com> Signed-off-by: Alexandre Julliard <julliard@winehq.org>
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@ -190,6 +190,7 @@ __ASM_GLOBAL_FUNC( do_cpuid,
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"pushl %ebx\n\t"
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"movl 12(%esp),%eax\n\t"
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"movl 16(%esp),%esi\n\t"
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"xorl %ecx,%ecx\n\t"
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"cpuid\n\t"
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"movl %eax,(%esi)\n\t"
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"movl %ebx,4(%esi)\n\t"
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@ -202,6 +203,7 @@ __ASM_GLOBAL_FUNC( do_cpuid,
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__ASM_GLOBAL_FUNC( do_cpuid,
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"pushq %rbx\n\t"
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"movl %edi,%eax\n\t"
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"xorl %ecx,%ecx\n\t"
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"cpuid\n\t"
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"movl %eax,(%rsi)\n\t"
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"movl %ebx,4(%rsi)\n\t"
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@ -277,7 +279,7 @@ static inline BOOL have_sse_daz_mode(void)
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static void get_cpuinfo( SYSTEM_CPU_INFORMATION *info )
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{
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unsigned int regs[4], regs2[4];
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unsigned int regs[4], regs2[4], regs3[4];
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#if defined(__i386__)
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info->Architecture = PROCESSOR_ARCHITECTURE_INTEL;
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@ -308,11 +310,21 @@ static void get_cpuinfo( SYSTEM_CPU_INFORMATION *info )
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if (regs2[3] & (1 << 25)) info->FeatureSet |= CPU_FEATURE_SSE;
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if (regs2[3] & (1 << 26)) info->FeatureSet |= CPU_FEATURE_SSE2;
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if (regs2[2] & (1 << 0 )) info->FeatureSet |= CPU_FEATURE_SSE3;
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if (regs2[2] & (1 << 9 )) info->FeatureSet |= CPU_FEATURE_SSSE3;
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if (regs2[2] & (1 << 13)) info->FeatureSet |= CPU_FEATURE_CX128;
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if (regs2[2] & (1 << 19)) info->FeatureSet |= CPU_FEATURE_SSE41;
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if (regs2[2] & (1 << 20)) info->FeatureSet |= CPU_FEATURE_SSE42;
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if (regs2[2] & (1 << 27)) info->FeatureSet |= CPU_FEATURE_XSAVE;
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if (regs2[2] & (1 << 28)) info->FeatureSet |= CPU_FEATURE_AVX;
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if((regs2[3] & (1 << 26)) && (regs2[3] & (1 << 24)) && have_sse_daz_mode()) /* has SSE2 and FXSAVE/FXRSTOR */
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info->FeatureSet |= CPU_FEATURE_DAZ;
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if (regs[0] >= 0x00000007)
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{
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do_cpuid( 0x00000007, regs3 ); /* get extended features */
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if (regs3[1] & (1 << 5)) info->FeatureSet |= CPU_FEATURE_AVX2;
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}
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if (regs[1] == AUTH && regs[3] == ENTI && regs[2] == CAMD)
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{
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info->Level = (regs2[0] >> 8) & 0xf; /* family */
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@ -928,6 +928,12 @@ typedef enum _HEAP_INFORMATION_CLASS {
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#define PF_RDPID_INSTRUCTION_AVAILABLE 33
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#define PF_ARM_V81_ATOMIC_INSTRUCTIONS_AVAILABLE 34
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#define PF_MONITORX_INSTRUCTION_AVAILABLE 35
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#define PF_SSSE3_INSTRUCTIONS_AVAILABLE 36
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#define PF_SSE4_1_INSTRUCTIONS_AVAILABLE 37
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#define PF_SSE4_2_INSTRUCTIONS_AVAILABLE 38
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#define PF_AVX_INSTRUCTIONS_AVAILABLE 39
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#define PF_AVX2_INSTRUCTIONS_AVAILABLE 40
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#define PF_AVX512F_INSTRUCTIONS_AVAILABLE 41
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/* Execution state flags */
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@ -1681,6 +1681,12 @@ typedef struct _SYSTEM_CPU_INFORMATION {
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#define CPU_FEATURE_NX 0x20000000 /* Data execution prevention */
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/* FIXME: following values are made up, actual flags are unknown */
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#define CPU_FEATURE_SSSE3 0x00008000 /* SSSE3 instructions */
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#define CPU_FEATURE_SSE41 0x01000000 /* SSE41 instructions */
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#define CPU_FEATURE_SSE42 0x02000000 /* SSE42 instructions */
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#define CPU_FEATURE_AVX 0x40000000 /* AVX instructions */
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#define CPU_FEATURE_AVX2 0x80000000 /* AVX2 instructions */
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#define CPU_FEATURE_PAE 0x00200000
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#define CPU_FEATURE_DAZ 0x00400000
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#define CPU_FEATURE_ARM_VFP_32 0x00000001
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@ -248,6 +248,7 @@ static void create_user_shared_data(void)
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features[PF_PAE_ENABLED] = !!(sci.FeatureSet & CPU_FEATURE_PAE);
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features[PF_XMMI64_INSTRUCTIONS_AVAILABLE] = !!(sci.FeatureSet & CPU_FEATURE_SSE2);
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features[PF_SSE3_INSTRUCTIONS_AVAILABLE] = !!(sci.FeatureSet & CPU_FEATURE_SSE3);
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features[PF_SSSE3_INSTRUCTIONS_AVAILABLE] = !!(sci.FeatureSet & CPU_FEATURE_SSSE3);
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features[PF_XSAVE_ENABLED] = !!(sci.FeatureSet & CPU_FEATURE_XSAVE);
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features[PF_COMPARE_EXCHANGE128] = !!(sci.FeatureSet & CPU_FEATURE_CX128);
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features[PF_SSE_DAZ_MODE_AVAILABLE] = !!(sci.FeatureSet & CPU_FEATURE_DAZ);
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@ -256,6 +257,10 @@ static void create_user_shared_data(void)
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features[PF_VIRT_FIRMWARE_ENABLED] = !!(sci.FeatureSet & CPU_FEATURE_VIRT);
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features[PF_RDWRFSGSBASE_AVAILABLE] = !!(sci.FeatureSet & CPU_FEATURE_RDFS);
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features[PF_FASTFAIL_AVAILABLE] = TRUE;
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features[PF_SSE4_1_INSTRUCTIONS_AVAILABLE] = !!(sci.FeatureSet & CPU_FEATURE_SSE41);
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features[PF_SSE4_2_INSTRUCTIONS_AVAILABLE] = !!(sci.FeatureSet & CPU_FEATURE_SSE42);
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features[PF_AVX_INSTRUCTIONS_AVAILABLE] = !!(sci.FeatureSet & CPU_FEATURE_AVX);
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features[PF_AVX2_INSTRUCTIONS_AVAILABLE] = !!(sci.FeatureSet & CPU_FEATURE_AVX2);
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break;
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case PROCESSOR_ARCHITECTURE_ARM:
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features[PF_ARM_VFP_32_REGISTERS_AVAILABLE] = !!(sci.FeatureSet & CPU_FEATURE_ARM_VFP_32);
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