winedbg: Add partial ARM disassembler.
This commit is contained in:
André Hentschel
Alexandre Julliard
parent
3b2fcdd426
commit
0fccc41c3f
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@ -24,6 +24,310 @@
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#if defined(__arm__) && !defined(__ARMEB__)
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/*
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* Switch to disassemble Thumb code.
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*/
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static BOOL db_disasm_thumb = FALSE;
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/*
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* Flag to indicate whether we need to display instruction,
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* or whether we just need to know the address of the next
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* instruction.
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*/
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static BOOL db_display = FALSE;
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#define ARM_INSN_SIZE 4
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#define THUMB_INSN_SIZE 2
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#define ROR32(n, r) (((n) >> (r)) | ((n) << (32 - (r))))
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#define get_cond(ins) tbl_cond[(ins >> 28) & 0x0f]
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#define get_nibble(ins, num) ((ins >> (num * 4)) & 0x0f)
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static char const tbl_addrmode[][3] = {
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"da", "ia", "db", "ib"
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};
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static char const tbl_cond[][3] = {
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"eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc", "hi", "ls", "ge", "lt", "gt", "le", "", ""
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};
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static char const tbl_dataops[][4] = {
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"and", "eor", "sub", "rsb", "add", "adc", "sbc", "rsc", "tst", "teq", "cmp", "cmn", "orr",
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"mov", "bic", "mvn"
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};
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static UINT db_get_inst(void* addr, int size)
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{
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UINT result = 0;
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char buffer[4];
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if (dbg_read_memory(addr, buffer, size))
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{
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switch (size)
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{
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case 4:
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result = *(UINT*)buffer;
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break;
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case 2:
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result = *(WORD*)buffer;
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break;
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}
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}
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return result;
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}
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static UINT arm_disasm_branch(UINT inst)
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{
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short link = (inst >> 24) & 0x01;
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int offset = (inst << 2) & 0x03ffffff;
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if (offset & 0x02000000) offset |= 0xfc000000;
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offset += 8;
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dbg_printf("\n\tb%s%s\t#%d/0x%08x", link ? "l" : "", get_cond(inst), offset, offset);
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return 0;
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}
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static UINT arm_disasm_dataprocessing(UINT inst)
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{
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short condcodes = (inst >> 20) & 0x01;
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short opcode = (inst >> 21) & 0x0f;
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short immediate = (inst >> 25) & 0x01;
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short no_op1 = (opcode & 0x0d) == 0x0d;
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/* check for nop */
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if (get_nibble(inst, 3) == 15 /* r15 */ && condcodes == 0 &&
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opcode >= 8 /* tst */ && opcode <= 11 /* cmn */)
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{
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dbg_printf("\n\tnop");
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return 0;
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}
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dbg_printf("\n\t%s%s%s", tbl_dataops[opcode], condcodes ? "s" : "", get_cond(inst));
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if (no_op1)
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{
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if (immediate)
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dbg_printf("\tr%u, #%u", get_nibble(inst, 3),
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ROR32(inst & 0xff, 2 * get_nibble(inst, 2)));
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else
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dbg_printf("\tr%u, r%u", get_nibble(inst, 3), get_nibble(inst, 0));
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}
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else
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{
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if (immediate)
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dbg_printf("\tr%u, r%u, #%u", get_nibble(inst, 3), get_nibble(inst, 4),
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ROR32(inst & 0xff, 2 * get_nibble(inst, 2)));
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else
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dbg_printf("\tr%u, r%u, r%u", get_nibble(inst, 3), get_nibble(inst, 4),
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get_nibble(inst, 0));
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}
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return 0;
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}
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static UINT arm_disasm_singletrans(UINT inst)
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{
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short load = (inst >> 20) & 0x01;
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short writeback = (inst >> 21) & 0x01;
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short byte = (inst >> 22) & 0x01;
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short direction = (inst >> 23) & 0x01;
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/* FIXME: what to do with bit 24 (indexing) */
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short immediate = !((inst >> 25) & 0x01);
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short offset = inst & 0x0fff;
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if (!direction) offset *= -1;
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dbg_printf("\n\t%s%s%s%s", load ? "ldr" : "str", byte ? "b" : "", writeback ? "t" : "",
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get_cond(inst));
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if (immediate)
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dbg_printf("\tr%u, [r%u, #%d]", get_nibble(inst, 3), get_nibble(inst, 4), offset);
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else
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dbg_printf("\tr%u, r%u, r%u", get_nibble(inst, 3), get_nibble(inst, 4),
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get_nibble(inst, 0));
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return 0;
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}
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static UINT arm_disasm_halfwordtrans(UINT inst)
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{
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short halfword = (inst >> 5) & 0x01;
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short sign = (inst >> 6) & 0x01;
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short load = (inst >> 20) & 0x01;
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short writeback = (inst >> 21) & 0x01;
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short immediate = (inst >> 22) & 0x01;
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short direction = (inst >> 23) & 0x01;
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/* FIXME: what to do with bit 24 (indexing) */
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short offset = ((inst >> 4) & 0xf0) + (inst & 0x0f);
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if (!direction) offset *= -1;
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dbg_printf("\n\t%s%s%s%s%s", load ? "ldr" : "str", sign ? "s" : "",
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halfword ? "h" : (sign ? "b" : ""), writeback ? "t" : "", get_cond(inst));
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if (immediate)
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dbg_printf("\tr%u, r%u, #%d", get_nibble(inst, 3), get_nibble(inst, 4), offset);
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else
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dbg_printf("\tr%u, r%u, r%u", get_nibble(inst, 3), get_nibble(inst, 4), get_nibble(inst, 0));
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return 0;
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}
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static UINT arm_disasm_blocktrans(UINT inst)
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{
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short load = (inst >> 20) & 0x01;
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short writeback = (inst >> 21) & 0x01;
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short psr = (inst >> 22) & 0x01;
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short addrmode = (inst >> 23) & 0x03;
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short i;
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short last=15;
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for (i=15;i>=0;i--)
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if ((inst>>i) & 1)
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{
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last = i;
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break;
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}
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dbg_printf("\n\t%s%s%s\tr%u%s, {", load ? "ldm" : "stm", tbl_addrmode[addrmode], get_cond(inst),
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get_nibble(inst, 4), writeback ? "!" : "");
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for (i=0;i<=15;i++)
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if ((inst>>i) & 1)
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{
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if (i == last) dbg_printf("r%u", i);
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else dbg_printf("r%u, ", i);
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}
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dbg_printf("}%s", psr ? "^" : "");
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return 0;
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}
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static UINT arm_disasm_swi(UINT inst)
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{
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UINT comment = inst & 0x00ffffff;
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dbg_printf("\n\tswi%s\t#%d/0x%08x", get_cond(inst), comment, comment);
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return 0;
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}
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static UINT arm_disasm_coproctrans(UINT inst)
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{
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WORD CRm = inst & 0x0f;
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WORD CP = (inst >> 5) & 0x07;
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WORD CPnum = (inst >> 8) & 0x0f;
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WORD CRn = (inst >> 16) & 0x0f;
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WORD load = (inst >> 20) & 0x01;
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WORD CP_Opc = (inst >> 21) & 0x07;
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dbg_printf("\n\t%s%s\t%u, %u, r%u, cr%u, cr%u, {%u}", load ? "mrc" : "mcr", get_cond(inst), CPnum,
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CP, get_nibble(inst, 3), CRn, CRm, CP_Opc);
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return 0;
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}
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static UINT arm_disasm_coprocdataop(UINT inst)
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{
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WORD CRm = inst & 0x0f;
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WORD CP = (inst >> 5) & 0x07;
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WORD CPnum = (inst >> 8) & 0x0f;
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WORD CRd = (inst >> 12) & 0x0f;
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WORD CRn = (inst >> 16) & 0x0f;
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WORD CP_Opc = (inst >> 20) & 0x0f;
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dbg_printf("\n\tcdp%s\t%u, %u, cr%u, cr%u, cr%u, {%u}", get_cond(inst),
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CPnum, CP, CRd, CRn, CRm, CP_Opc);
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return 0;
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}
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static UINT arm_disasm_coprocdatatrans(UINT inst)
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{
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WORD CPnum = (inst >> 8) & 0x0f;
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WORD CRd = (inst >> 12) & 0x0f;
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WORD load = (inst >> 20) & 0x01;
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/* FIXME: what to do with bit 21 (writeback) */
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WORD translen = (inst >> 22) & 0x01;
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WORD direction = (inst >> 23) & 0x01;
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/* FIXME: what to do with bit 24 (indexing) */
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short offset = (inst & 0xff) << 2;
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if (!direction) offset *= -1;
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dbg_printf("\n\t%s%s%s", load ? "ldc" : "stc", translen ? "l" : "", get_cond(inst));
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dbg_printf("\t%u, cr%u, [r%u, #%d]", CPnum, CRd, get_nibble(inst, 4), offset);
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return 0;
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}
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struct inst_arm
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{
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UINT mask;
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UINT pattern;
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UINT (*func)(UINT);
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};
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static const struct inst_arm tbl_arm[] = {
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{ 0x0e000000, 0x0a000000, arm_disasm_branch },
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{ 0x0c000000, 0x00000000, arm_disasm_dataprocessing },
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{ 0x0c000000, 0x04000000, arm_disasm_singletrans },
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{ 0x0e000090, 0x00000090, arm_disasm_halfwordtrans },
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{ 0x0e000000, 0x08000000, arm_disasm_blocktrans },
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{ 0x0f000000, 0x0f000000, arm_disasm_swi },
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{ 0x0f000010, 0x0e000010, arm_disasm_coproctrans },
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{ 0x0f000010, 0x0e000000, arm_disasm_coprocdataop },
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{ 0x0e000000, 0x0c000000, arm_disasm_coprocdatatrans },
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{ 0x00000000, 0x00000000, NULL }
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};
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/***********************************************************************
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* disasm_one_insn
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*
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* Disassemble instruction at 'addr'. addr is changed to point to the
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* start of the next instruction.
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*/
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void be_arm_disasm_one_insn(ADDRESS64 *addr, int display)
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{
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struct inst_arm *a_ptr = (struct inst_arm *)&tbl_arm;
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UINT inst;
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int size;
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int matched = 0;
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char tmp[64];
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DWORD_PTR* pval;
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if (!memory_get_register(CV_ARM_CPSR, &pval, tmp, sizeof(tmp)))
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dbg_printf("\n\tmemory_get_register failed: %s\n",tmp);
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else
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db_disasm_thumb=(*pval & 0x20)?TRUE:FALSE;
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if (db_disasm_thumb) size = THUMB_INSN_SIZE;
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else size = ARM_INSN_SIZE;
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db_display = display;
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inst = db_get_inst( memory_to_linear_addr(addr), size );
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if (!db_disasm_thumb)
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{
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while (a_ptr->func) {
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if ((inst & a_ptr->mask) == a_ptr->pattern) {
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matched = 1;
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break;
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}
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a_ptr++;
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}
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if (!matched) {
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dbg_printf("\n\tUnknown Instruction: %08x\n", inst);
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addr->Offset += size;
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return;
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}
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else
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{
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if (!a_ptr->func(inst))
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{
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dbg_printf("\n");
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addr->Offset += size;
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}
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return;
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}
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}
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else
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{
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dbg_printf("\n\tThumb disassembling not yet implemented\n");
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addr->Offset += size;
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}
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}
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static unsigned be_arm_get_addr(HANDLE hThread, const CONTEXT* ctx,
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enum be_cpu_addr bca, ADDRESS64* addr)
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{
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@ -150,11 +454,6 @@ static unsigned be_arm_is_jump(const void* insn, ADDRESS64* jumpee)
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return FALSE;
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}
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static void be_arm_disasm_one_insn(ADDRESS64* addr, int display)
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{
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dbg_printf("Disasm NIY\n");
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}
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static unsigned be_arm_insert_Xpoint(HANDLE hProcess, const struct be_process_io* pio,
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CONTEXT* ctx, enum be_xpoint_type type,
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void* addr, unsigned long* val, unsigned size)
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